公开(公告)号：US6058501A

公开(公告)日：2000-05-02

申请号：US998838

申请日：1997-12-29

Applicant: Koichi Urazoe ,  Toshimitsu Nakahara

Inventor： Koichi Urazoe ,  Toshimitsu Nakahara

IPC: H03M13/23 ,  H04L1/00 ,  H03M13/00 ,  H03M13/12

CPC classification number: H04L1/201 ,  H04L1/0054 ,  H04L1/0061

Abstract: An error detecting device of received digital data solves a problem for detecting errors in a conventional device in that error detection following the Viterbi decoding performed on most important bits cannot detect errors even if they include a considerable amount of errors, and that odd sounds result from decoding of voice data, for example. The present error detecting device includes a Viterbi decoder for carrying out the Viterbi decoding of the received digital data, an error number decision portion for comparing a threshold value with the number of errors of the path metric obtained by the Viterbi decoding, and a voice decoder for decoding the received digital data, on which the error number decision portion decides that the number of errors is below the threshold value.

Abstract translation: 接收到的数字数据的错误检测装置解决了常规装置中检测错误的问题，因为在最重要的位执行的维特比解码之后的错误检测不能检测错误，即使它们包括相当大量的错误，并且奇数声音由 语音数据的解码。 本错误检测装置包括：维特比解码器，用于对所接收的数字数据执行维特比解码;错误数决定部分，用于将阈值与通过维特比解码获得的路径度量的误差数进行比较;以及语音解码器 用于对接收到的数字数据进行解码，其中错误号决定部分决定错误数量低于阈值。

公开(公告)号：US6052821A

公开(公告)日：2000-04-18

申请号：US11565

申请日：1998-02-13

Applicant: Antoine Chouly ,  Americo Brajal ,  David Gianella

Inventor： Antoine Chouly ,  Americo Brajal ,  David Gianella

IPC: H03M13/23 ,  H04L27/34 ,  H03M13/12

CPC classification number: H04L27/3433

Abstract: A digital transmission system provides selective protection by combining a convolutional coding, a punctured coding and a digital quadrature amplitude modulation. The rate of the convolutional coding in N/2N and the modulation uses a 2.sup.2N -point constellation, with N>1.

Abstract translation: PCT No.PCT / IB97 / 00756 Sec。 371日期1998年2月13日 102（e）日期1998年2月13日PCT提交1997年6月23日PCT公布。 出版物WO97 / 50218 PCT 日期1997年12月31日数字传输系统通过组合卷积编码，打孔编码和数字正交幅度调制来提供选择性保护。 N / 2N中的卷积编码速率和调制采用22N点星座，N> 1。

公开(公告)号：US06044486A

公开(公告)日：2000-03-28

申请号：US929151

申请日：1997-09-11

Applicant: Mark Underseth ,  Nobusuke Matsuoka

Inventor： Mark Underseth ,  Nobusuke Matsuoka

IPC: H04L1/08 ,  G06F11/10 ,  H03M13/12

CPC classification number: H04L1/08

Abstract: A method and device for error-correcting a plurality of bits transmitted over RF channels in a cellular communication system are provided. The present invention applies principles of majority voting to error-correct a plurality of bits in a message word simultaneously. Further, the present invention applies its error-correction capability to virtually any number of repeat transmissions over forward and reverse control/voice channels. Following synchronization of the transmit and receive stations, a message word having n-bits is transmitted repeatedly. The repeat bits are separated and analyzed whereafter the true logical state of the original n-bits is determined. The originally transmitted message word is then reconstructed based upon the determined true logical state of the n-bits.

Abstract translation: 提供了一种用于在蜂窝通信系统中通过RF信道发送的多个比特进行纠错的方法和装置。 本发明应用多数投票原则同时对消息字中的多个位进行错误校正。 此外，本发明通过正向和反向控制/语音信道将其纠错能力应用于几乎任何数量的重复传输。 在发送站和接收站同步之后，重复发送具有n位的消息字。 重复位被分离并分析，然后确定原始n位的真实逻辑状态。 然后基于所确定的n位的真实逻辑状态来重建原始传输的消息字。

公开(公告)号：US06044116A

公开(公告)日：2000-03-28

申请号：US182446

申请日：1998-10-29

Applicant: Charles C. Wang

Inventor： Charles C. Wang

IPC: H03M13/29 ,  H04L5/12 ,  H03M13/12

CPC classification number: H03M13/6356 ,  H03M13/2903 ,  H03M13/2957 ,  H03M13/6362

Abstract: The turbo coding system combines: a) repetitive turbo encoder bit partitioning and decoder bit deletion; with b) error-floor mitigating encoder non-flushing the second constituent encoder with the second a-posteriori probability (APP) decoder starting backward recursion from any possible states as a powerful improvement to conventional turbo coding. The repetitive turbo encoding process repeats the bits of the systematic root sequence and appends flushing sequence prior to interleaving and encoding by the second constituent turbo encoder for providing an interleaved repetitive second encoded output for turbo decoding. The error-floor mitigating turbo encoding process does not flush the second constituent encoder to the zero ending state so that turbo decoding forward recursion may be end in any possible state and backward recursion may start from any possible state to avoid potential mismatches between the forward and backward recursions. The modified a posterior probability second decoder initializes the beginning state metric of the backward recursion with the ending state metric of the forward recursion. The two processes provide significant bit error rate improvement. Iterative decoding provides iterative results that are subject to majority voting selection for improved estimations of the decoded systematic data sequence.

Abstract translation: turbo编码系统结合：a）重复turbo编码器比特分配和解码器位删除; 其中b）错误地减轻编码器，使用第二个后验概率（APP）解码器从任何可能的状态开始向后递归而不冲洗第二组成编码器，作为对常规turbo编码的强大改进。 重复turbo编码过程重复系统根序列的比特并且在由第二组成turbo编码器进行交织和编码之前附加冲洗序列，以提供用于turbo解码的交织重复的第二编码输出。 错误层减轻turbo编码过程不会将第二组成编码器刷新为零结束状态，使得turbo解码正向递归可以在任何可能的状态结束，并且向后递归可以从任何可能的状态开始，以避免前向和后向递归之间的潜在的不匹配 向后递归。 修改的后验概率第二解码器以正向递归的结束状态度量初始化反向递归的开始状态度量。 这两个过程提供了显着的误码率改进。 迭代解码提供了经过多数表决选择的迭代结果，用于改进解码的系统数据序列的估计。

公开(公告)号：US6041433A

公开(公告)日：2000-03-21

申请号：US833483

申请日：1997-04-07

Applicant: Takehiro Kamada

Inventor： Takehiro Kamada

IPC: H03M13/23 ,  H03M13/41 ,  H03M13/00 ,  H03M13/12

CPC classification number: H03M13/6502 ,  H03M13/4107 ,  H03M13/4169 ,  H03M13/6505

Abstract: The present invention provides an improved Viterbi decoder with a trace-back memory that requires a much less storage capacity required for signal decoding processing as compared with a commonly-used trace-back memory. Based on an input received code, an add-compare-select (ACS) circuit generates path select (PS) signals, and m generated PS signals per unit are written into a path storing means and are fed to a starting node number deciding circuit where the number m indicates a trace-back length. The starting node number deciding circuit finds from the m PS signals a trace-back starting node number for a PS signal preceding the m PS signals. PS signals are read out from the path storing means, trace-back processing starts from the starting node number found by the starting node number deciding circuit, and signal decoding processing is carried out. This eliminates the need for providing a state of performing provisional trace-back processing for finding a starting node number, thereby reducing the number of states necessary for the decoding of signals from four down to three. This reduces the storage capacity of memory required for storing PS signals and thereby achieves a considerable reduction of the circuit size.

Abstract translation: 本发明提供了一种具有追溯存储器的改进的维特比解码器，其与常用的追溯存储器相比需要比信号解码处理所需的更少的存储容量。 基于输入接收码，加法比较选择（ACS）电路产生路径选择（PS）信号，并且每单位的m个生成的PS信号被写入路径存储装置，并被馈送到起始节点号决定电路，其中 数字m表示追溯长度。 起始节点号决定电路从m PS信号中找出用于m PS信号之前的PS信号的追溯起始节点号。 从路径存储装置读出PS信号，从起始节点号决定电路所发现的起始节点编号开始追踪处理，进行信号解码处理。 这消除了提供执行用于查找起始节点号码的临时追溯处理的状态的需要，从而减少了信号从4个到3个解码所需的状态数量。 这降低了存储PS信号所需的存储器的存储容量，从而实现了电路尺寸的显着降低。

公开(公告)号：US5983383A

公开(公告)日：1999-11-09

申请号：US786952

申请日：1997-01-17

Applicant: Jack K. Wolf

Inventor： Jack K. Wolf

IPC: H03M13/15 ,  H03M13/29 ,  H03M13/41 ,  H03M13/47 ,  H04L1/00 ,  H04L1/16 ,  H03M13/00 ,  H03M13/12

CPC classification number: H04L1/0057 ,  H03M13/29 ,  H03M13/47 ,  H04L1/0054 ,  H04L1/0065 ,  H04L1/0071 ,  H04L1/16

Abstract: In a concatenated code data, correctly decoded code words from a block decoder is utilized to improve the performance of the convolutional decoder. A code word can sometimes be correctly decoded prior to receipt of all the symbols for the code word. Early decoding of the code word allows for the correct recreation of the entire code word, even the symbols which have not yet been received. The entire corrected code word is used by the convolutional decoder to eliminate branches the trellis, thus improving decoding of prior data bits and future data bits in the trellis. The chain back distance of the convolutional decoder can also be made shorter based on the knowledge that some of the received code words have been correctly decoded. Finally, the parity symbols which have not yet been received for the correctly decoded code word can be eliminated from transmission to improve the overall transmission rate.

Abstract translation: 在级联代码数据中，利用来自块解码器的正确解码的码字来提高卷积解码器的性能。 有时可以在接收到代码字的所有符号之前对代码字进行正确解码。 代码字的早期解码允许对整个代码字的正确重构，甚至是尚未被接收的符号。 整个纠错码字被卷积解码器用于消除网格分支，从而改善了网格中先前数据位和未来数据位的解码。 基于一些接收到的代码字已经被正确解码的知识，卷积解码器的链回距离也可以缩短。 最后，可以从传输中消除尚未被接收到用于正确解码的码字的奇偶校验符号，以提高整体传输速率。

公开(公告)号：US5968201A

公开(公告)日：1999-10-19

申请号：US834838

申请日：1997-04-10

Applicant: Kazuo Shida ,  Mitsuru Uesugi

Inventor： Kazuo Shida ,  Mitsuru Uesugi

IPC: G11B20/18 ,  H03M13/00 ,  H03M13/29 ,  H03M13/37 ,  H04B14/04 ,  G06F11/10 ,  H03M13/12

CPC classification number: H03M13/2927 ,  H03M13/00 ,  H03M13/23 ,  H03M13/29 ,  H03M13/41

Abstract: Received data representing voice information is subjected to Viterbi decoding to correct an error in the received data. Thereby, the received data is decoded into second data. A path metric is calculated to determine the second data during the Viterbi decoding. A decision is made as to whether or not at least one error is present in the second data by referring to a cyclic redundancy check code in the second data. The second data is discarded when it is decided that at least one error is present in the second data. A decision is made as to whether or not the calculated path metric exceeds a threshold value. The second data is discarded when it is decided that the path metric exceeds the threshold value. The second data is converted into sound when it is decided that at least one error is not present in the second data and that the path metric does not exceed the threshold value.

Abstract translation: 代表语音信息的接收数据进行维特比解码以校正接收到的数据中的错误。 由此，接收的数据被解码为第二数据。 计算路径度量以在维特比解码期间确定第二数据。 通过参考第二数据中的循环冗余校验码来决定第二数据中是否存在至少一个错误。 当确定在第二数据中存在至少一个错误时，丢弃第二数据。 作出关于所计算的路径度量是否超过阈值的决定。 当确定路径度量超过阈值时，第二数据被丢弃。 当确定在第二数据中不存在至少一个错误并且路径度量不超过阈值时，第二数据被转换成声音。

公开(公告)号：US5960011A

公开(公告)日：1999-09-28

申请号：US159636

申请日：1998-09-24

Applicant: Dae-Il Oh

Inventor： Dae-Il Oh

IPC: H03M13/23 ,  H03M13/33 ,  H03M13/41 ,  H04L7/00 ,  G06F11/10 ,  H03M13/12

CPC classification number: H03M13/4169 ,  H03M13/41 ,  H03M13/4107 ,  H03M13/6362 ,  H03M13/6502

Abstract: A viterbi decoder includes a maximum branch metric value detecting device separated from a feedback loop consisting of an ACS arithmetic unit, a normalization arithmetic unit, and a state value storing device. In operation, a maximum branch metric value is detected by utilizing the output of the state value storing device, to thereby enhance operating speed. Further, a judgment is made as to whether a state having the minimum state value at an immediately preceding time is back-traceable from a state having the minimum state value at a current time by using survivor path information. Non-back-traceable non-correspondences are then detected, and the number of occurrences of non-correspondences are counted. If the occurrences of non-correspondences exceed a reference value, it is judged a non-synchronization. In another method, synchronization/non-synchronization is judged by detecting whether a trace back is possible, without utilizing survivor path information.

Abstract translation: 维特比解码器包括与由ACS运算单元，归一化运算单元和状态值存储装置组成的反馈回路分离的最大支路量度值检测装置。 在操作中，通过利用状态值存储装置的输出来检测最大分支度量值，从而提高操作速度。 此外，通过使用幸存路径信息，判断在当前时刻从具有最小状态值的状态在紧邻的前一时刻具有最小状态值的状态是否可追溯。 然后检测到不可追溯的非对应关系，并计数非对应的出现次数。 如果非对应的事件超过参考值，则判断为不同步。 在另一种方法中，通过检测是否可以追溯来判断同步/非同步，而不利用幸存者路径信息。

公开(公告)号：US5896405A

公开(公告)日：1999-04-20

申请号：US588698

申请日：1996-01-19

Applicant: Heon-hee Moon

Inventor： Heon-hee Moon

IPC: H04L1/00 ,  H04L27/38 ,  G06F11/10 ,  H03M13/12

CPC classification number: H04L1/0047 ,  H04L1/0054 ,  H04L1/0071 ,  H04L27/38

Abstract: An apparatus for receiving data block-interleaved and multi level/phase modulated data and restoring the block-interleaved multi level/phase modulated data into original data, comprises a demodulation and error correction portion for demodulating and error-correcting data to be received and outputting the modulated and error-corrected data; a synchronization portion for generating a fixed sync position signal, based on the comparison between the data output from the demodulation and error correction portion and stored block sync data; and a block deinterleaver for block-deinterleaving the data which is output from the demodulation and error correction portion according to the fixed sync position signal. The apparatus makes certain that a sync signal for block deinterleaving is identical to a sync signal at the transmission end and performs block deinterleaving even though no error correction is made. Furthermore, the present invention is capable of reliably detecting a sync signal, even when the sync signal is momentarily deviated because error correction is not completely made.

Abstract translation: 一种用于接收数据块交错和多电平/相位调制数据并将块交织的多电平/相位调制数据恢复为原始数据的装置，包括用于解调和纠错待接收数据的解调和纠错部分，并输出 调制和纠错数据; 基于从解调和纠错部分输出的数据与存储的块同步数据之间的比较产生固定同步位置信号的同步部分; 以及块解交织器，用于根据固定同步位置信号块解交织从解调和纠错部分输出的数据。 该装置确定用于块去交织的同步信号与发送端的同步信号相同，并且即使没有进行纠错，也执行块去交织。 此外，即使由于错误校正不完全而使同步信号暂时偏离，本发明也能够可靠地检测同步信号。

公开(公告)号：US5809089A

公开(公告)日：1998-09-15

申请号：US605749

申请日：1996-02-22

Applicant: Dobrica Vasic

Inventor： Dobrica Vasic

IPC: H04J13/00 ,  H03M13/23 ,  H03M13/45 ,  H04B1/711 ,  H04L1/00 ,  H04L1/02 ,  H03M13/12

CPC classification number: H04B1/7115 ,  H04L1/0054

Abstract: The present invention comprises: M units of Bessel function calculation means for inputting M signals X.sub.1 to X.sub.M that are produced by performing a reception signal high-speed Hadamard's transformation and outputting M modified Bessel functions Y.sub.1 to Y.sub.M corresponding to the signals; and K units of bit metric calculation means having addition means for adding the modified Bessel functions Y.sub.1 to Y.sub.M to each bit of k bits according to codes that are determined for cases of assumption that 0 is transmitted and 1 is transmitted and logarithm calculation means for calculating logarithm of output from the addition means for obtaining soft information.

Abstract translation: 本发明包括：M个贝塞尔函数计算装置，用于输入通过执行接收信号高速哈达玛变换产生的M个信号X1至XM，并输出对应于该信号的M个改进的贝塞尔函数Y1至YM; 和K个比特度量计算单元，具有用于根据在发送0和发送1的情况下确定的代码将修改的贝塞尔函数Y1至YM添加到每个比特的比特的附加装置，以及用于计算的对数计算装置 用于获得软信息的加法装置的输出对数。