公开(公告)号：US08027797B2

公开(公告)日：2011-09-27

申请号：US12110639

申请日：2008-04-28

申请人： Manjul Bhushan ,  Mark B. Ketchen ,  Dale J. Pearson

发明人： Manjul Bhushan ,  Mark B. Ketchen ,  Dale J. Pearson

IPC分类号： G01R25/00

CPC分类号： G01R31/31707 ,  G01R31/3016 ,  G01R31/31708 ,  H03K5/04

摘要： Techniques for inline measurement of a switching history time constant in an integrated circuit device are provided. A series of pulses is launched into a first stage of a delay chain comprising a plurality of delay stages connected in series and having a length greater than a decay length of at least an initial one of the series of pulses, such that the at least initial one of the series of pulses does not appear at a second stage of the delay chain. An amount of time between the launching of the initial one of the series of pulses and the appearance of at least one of the series of pulses at the second stage of the delay chain is determined. The switching history time constant is calculated as a function of a number of stages traversed by the at least one pulse, the determined amount of time, and the decay length of the at least initial one of the series of pulses based at least in part on a switching history of the integrated circuit device.

摘要翻译： 提供了用于集成电路装置中的切换历史时间常数的在线测量的技术。 一系列脉冲被发射到延迟链的第一级中，该延迟链包括多个串联连接的延迟级，其长度大于该系列脉冲中的至少初始脉冲的衰减长度，使得至少初始 一系列脉冲之一不出现在延迟链的第二阶段。 确定在延迟链的第二阶段发射一系列脉冲中的初始脉冲之一和至少一个脉冲串的出现之间的时间量。 切换历史时间常数被计算为至少部分地基于至少一个脉冲遍历的次数的数量，所确定的时间量以及该系列脉冲中的至少初始脉冲的衰减长度的函数 集成电路装置的切换历史。

公开(公告)号：US20090271134A1

公开(公告)日：2009-10-29

申请号：US12110639

申请日：2008-04-28

申请人： Manjul Bhushan ,  Mark B. Ketchen ,  Dale J. Pearson

发明人： Manjul Bhushan ,  Mark B. Ketchen ,  Dale J. Pearson

IPC分类号： G01R29/00

CPC分类号： G01R31/31707 ,  G01R31/3016 ,  G01R31/31708 ,  H03K5/04

摘要： Techniques for inline measurement of a switching history time constant in an integrated circuit device are provided. A series of pulses is launched into a first stage of a delay chain comprising a plurality of delay stages connected in series and having a length greater than a decay length of at least an initial one of the series of pulses, such that the at least initial one of the series of pulses does not appear at a second stage of the delay chain. An amount of time between the launching of the initial one of the series of pulses and the appearance of at least one of the series of pulses at the second stage of the delay chain is determined. The switching history time constant is calculated as a function of a number of stages traversed by the at least one pulse, the determined amount of time, and the decay length of the at least initial one of the series of pulses based at least in part on a switching history of the integrated circuit device.

摘要翻译： 提供了用于集成电路装置中的切换历史时间常数的在线测量的技术。 一系列脉冲被发射到延迟链的第一级中，该延迟链包括多个串联连接的延迟级，其长度大于该系列脉冲中的至少初始脉冲的衰减长度，使得至少初始 一系列脉冲之一不出现在延迟链的第二阶段。 确定在延迟链的第二阶段发射一系列脉冲中的初始脉冲之一和至少一个脉冲串的出现之间的时间量。 切换历史时间常数被计算为至少部分地基于至少一个脉冲遍历的次数的数量，所确定的时间量以及该系列脉冲中的至少初始脉冲的衰减长度的函数 集成电路装置的切换历史。

公开(公告)号：US06798261B1

公开(公告)日：2004-09-28

申请号：US10443515

申请日：2003-05-22

申请人： Manjul Bhushan ,  Mark B. Ketchen ,  Dale J. Pearson

发明人： Manjul Bhushan ,  Mark B. Ketchen ,  Dale J. Pearson

IPC分类号： H03K3017

CPC分类号： H03K5/26 ,  H03K5/13

摘要： A method for characterizing a change in delay induced by a switching history of a circuit includes the steps of generating a first signal having a pulse width that is selectively adjustable, the first signal having a first edge and a second edge associated therewith, the first and second edges being opposite in polarity with respect to one another; generating a second signal having a first switch delay characteristic of the first edge of the first signal and a second switch delay characteristic of the second edge of the first signal, wherein the pulse width of the first signal is less than the first switch delay associated with the second signal; varying the pulse width of the first signal; monitoring the second signal; determining a value of the pulse width that defines a boundary of when the second signal is present and when the second signal is not present; and determining a ratio of the value of the pulse width that defines the boundary to the first switch delay and/or the second switch delay, whereby the change in delay induced by the switching history of the circuit to be characterized is a function of the ratio.

摘要翻译： 用于表征由电路的切换历史引起的延迟变化的方法包括以下步骤：产生具有可选择性调节的脉冲宽度的第一信号，第一信号具有与其相关联的第一边缘和第二边缘，第一和 第二边缘相对于彼此的极性相反; 产生具有第一信号的第一边缘的第一开关延迟特性和第一信号的第二边沿的第二开关延迟特性的第二信号，其中第一信号的脉冲宽度小于与第一信号相关联的第一开关延迟 第二个信号; 改变第一信号的脉冲宽度; 监测第二信号; 确定限定所述第二信号存在时和所述第二信号不存在的边界的所述脉冲宽度的值; 并且确定限定边界的脉冲宽度与第一开关延迟和/或第二开关延迟的比值，由此由要表征的电路的开关历史引起的延迟变化是该比率的函数 。

公开(公告)号：US20110169499A1

公开(公告)日：2011-07-14

申请号：US12686476

申请日：2010-01-13

申请人： Manjul Bhushan ,  Mark B. Ketchen ,  Qingqing Liang ,  Edward P. Maciejewski

发明人： Manjul Bhushan ,  Mark B. Ketchen ,  Qingqing Liang ,  Edward P. Maciejewski

IPC分类号： G01R31/02 ,  G01R19/00

CPC分类号： G01R31/2856 ,  G01R31/2894

摘要： A test structure is provided that utilizes a time division sampling technique along with a statistical modeling technique that uses metal-oxide-semiconductor field effect transistor (MOSFET) saturation and linear characteristics to measure the mean (average) and sigma (statistical characterization of the variation) of a large population of electrical characteristics of electrical devices (e.g., integrated circuits) at high speed. Such electrical characteristics or sampling parameters include drive currents, leakage, resistances, etc.

摘要翻译： 提供了一种测试结构，其利用时分采样技术以及使用金属氧化物半导体场效应晶体管（MOSFET）饱和度和线性特性的统计建模技术来测量平均值（平均）和σ（变化的统计特征） ）高速电气设备（如集成电路）的大量电气特性。 这种电气特性或采样参数包括驱动电流，泄漏，电阻等

公开(公告)号：US20110043242A1

公开(公告)日：2011-02-24

申请号：US12544772

申请日：2009-08-20

申请人： Manjul Bhushan ,  Mark B. Ketchen

发明人： Manjul Bhushan ,  Mark B. Ketchen

IPC分类号： G01R31/26 ,  G01R31/02

CPC分类号： G01R31/31725 ,  G01R31/31727

摘要： A test structure for gathering switching history effect statistics includes a waveform generator circuit that selectively generates a first test waveform representative of a 1SW transistor switching event, and a second test waveform representative of a 2SW transistor switching event; and a history element circuit coupled to the waveform generator circuit, the history element circuit including a device under test (DUT) therein, and a variable delay chain therein, wherein a selected one of the first and second test waveforms are input to the DUT and the variable delay chain; wherein the history element circuit determines fractional a change in signal propagation delay through the DUT between the 1SW and 2SW transistor switching events, with the fractional change in signal propagation delay calibrated with timing measurements of a variable frequency ring oscillator; and wherein the test structure utilizes only external low-speed input and output signals with respect to a chip.

摘要翻译： 用于采集切换历史效果统计的测试结构包括：选择性地产生代表1SW晶体管切换事件的第一测试波形的波形发生器电路和代表2SW晶体管切换事件的第二测试波形; 以及耦合到所述波形发生器电路的历史元件电路，所述历史元件电路包括其中的被测器件（DUT）及其中的可变延迟链，其中所述第一和第二测试波形中的所选择的一个输入到所述DUT， 可变延迟链; 其中历史元件电路通过在1SW和2SW晶体管切换事件之间通过DUT的信号传播延迟的变化来确定分数，其中通过可变频率环形振荡器的定时测量校准信号传播延迟的分数变化; 并且其中测试结构仅利用相对于芯片的外部低速输入和输出信号。

公开(公告)号：US07583125B2

公开(公告)日：2009-09-01

申请号：US11923916

申请日：2007-10-25

申请人： Manjul Bhushan ,  Mark B. Ketchen ,  Chandrasekharan Kothandaraman ,  Edward P. Maciejewski

发明人： Manjul Bhushan ,  Mark B. Ketchen ,  Chandrasekharan Kothandaraman ,  Edward P. Maciejewski

IPC分类号： H03K3/00

CPC分类号： G01R31/31853 ,  G01R31/30 ,  G01R31/3004

摘要： An integrated circuit device having at least one fuse capable of being blown in order to provide measurements of fuse current-voltage characteristics is provided. The integrated circuit device also provides at least one pulse generation circuit associated with the fuse and capable of generating a pulse to blow the fuse through one or more DC input signals.

摘要翻译： 提供一种具有至少一个能够被熔断以便提供熔丝电流 - 电压特性测量的熔断器的集成电路器件。 集成电路装置还提供与熔丝相关联的至少一个脉冲发生电路，并且能够产生脉冲以通过一个或多个DC输入信号来熔断熔丝。

公开(公告)号：US20080142848A1

公开(公告)日：2008-06-19

申请号：US12041388

申请日：2008-03-03

申请人： Manjul Bhushan ,  Karen M.G.V. Gettings ,  Wilfried E. Haensch ,  Brian L. Ji ,  Mark B. Ketchen

发明人： Manjul Bhushan ,  Karen M.G.V. Gettings ,  Wilfried E. Haensch ,  Brian L. Ji ,  Mark B. Ketchen

IPC分类号： H01L27/088

CPC分类号： G01R31/2884 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit device is provided including at least one first array configuration of integrated circuit components comprising a m×n array of FETs, without specified internal connections between the integrated circuit components, wherein m is greater than two. The integrated circuit device further includes at least one second array configuration of integrated circuit components comprising an array of integrated circuit components nominally identical to those of the first array configuration, with specified internal connections between integrated circuit components. A variation coefficient is determined for the integrated circuit components based on a measured specified parameter of the first array configuration and the second array configuration.

摘要翻译： 提供一种集成电路器件，其包括至少一个集成电路部件的第一阵列结构，该集成电路部件包括一组FET，该集成电路阵列在集成电路部件之间没有规定的内部连接，其中m大于2。 集成电路装置还包括集成电路部件的至少一个第二阵列配置，其包括与第一阵列配置的名义上相同的集成电路组件的阵列，以及集成电路部件之间的指定的内部连接。 基于第一阵列配置和第二阵列配置的测量的指定参数来确定集成电路组件的变化系数。

公开(公告)号：US08456169B2

公开(公告)日：2013-06-04

申请号：US12686476

申请日：2010-01-13

申请人： Manjul Bhushan ,  Mark B. Ketchen ,  Qingqing Liang ,  Edward P. Maciejewski

发明人： Manjul Bhushan ,  Mark B. Ketchen ,  Qingqing Liang ,  Edward P. Maciejewski

IPC分类号： G01R31/02

CPC分类号： G01R31/2856 ,  G01R31/2894

摘要： A test structure is provided that utilizes a time division sampling technique along with a statistical modeling technique that uses metal-oxide-semiconductor field effect transistor (MOSFET) saturation and linear characteristics to measure the mean (average) and sigma (statistical characterization of the variation) of a large population of electrical characteristics of electrical devices (e.g., integrated circuits) at high speed. Such electrical characteristics or sampling parameters include drive currents, leakage, resistances, etc.

摘要翻译： 提供了一种测试结构，其利用时分采样技术以及使用金属氧化物半导体场效应晶体管（MOSFET）饱和度和线性特性的统计建模技术来测量平均值（平均）和σ（变化的统计特征） ）高速电气设备（如集成电路）的大量电气特性。 这种电气特性或采样参数包括驱动电流，泄漏，电阻等

公开(公告)号：US20120166898A1

公开(公告)日：2012-06-28

申请号：US13410865

申请日：2012-03-02

申请人： Manjul Bhushan ,  Mark B. Ketchen ,  Chin Kim

发明人： Manjul Bhushan ,  Mark B. Ketchen ,  Chin Kim

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/31725 ,  G01R31/3016

摘要： A test structure for an integrated circuit device includes one or more experiments selectively configured to receive one or more high-speed input signals as inputs thereto and to output at least one high-speed output signal therefrom, the one or more experiments each including two or more logic gates configured to determine differential delay characteristics of individual circuit devices, at a precision level on the order of picoseconds to less than 1 picosecond; and wherein the one or more sets of experiments are disposed, and are fully testable, at a first level of metal wiring (Ml) in the integrated circuit device.

摘要翻译： 用于集成电路装置的测试结构包括一个或多个实验，其被选择性地配置为接收一个或多个高速输入信号作为其输入并从其输出至少一个高速输出信号，所述一个或多个实验各自包括两个或 多个逻辑门被配置为确定各个电路装置的差分延迟特性，其精度水平以皮秒级小于1皮秒; 并且其中所述一组或多组实验在所述集成电路器件中的金属布线（M1）的第一级处被布置并且是完全可测试的。

公开(公告)号：US20120161807A1

公开(公告)日：2012-06-28

申请号：US13410851

申请日：2012-03-02

申请人： Manjul Bhushan ,  Mark B. Ketchen ,  Chin Kim

发明人： Manjul Bhushan ,  Mark B. Ketchen ,  Chin Kim

IPC分类号： G01R31/26

CPC分类号： G01R31/31725 ,  G01R31/3016

摘要： A test structure for an integrated circuit device includes one or more experiments selectively configured to receive one or more high-speed input signals as inputs thereto and to output at least one high-speed output signal therefrom, the one or more experiments each including two or more logic gates configured to determine differential delay characteristics of individual circuit devices, at a precision level on the order of picoseconds to less than 1 picosecond; and wherein the one or more sets of experiments are disposed, and are fully testable, at a first level of metal wiring (M1) in the integrated circuit device.

摘要翻译： 用于集成电路装置的测试结构包括一个或多个实验，其被选择性地配置为接收一个或多个高速输入信号作为其输入并从其输出至少一个高速输出信号，所述一个或多个实验各自包括两个或 多个逻辑门被配置为确定各个电路装置的差分延迟特性，其精度水平以皮秒级小于1皮秒; 并且其中所述一组或多组实验在所述集成电路装置中的金属布线（M1）的第一级处被布置并且是完全可测试的。