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    HIGH SPEED MEASUREMENT OF RANDOM VARIATION/YIELD IN INTEGRATED CIRCUIT DEVICE TESTING
    1.
    发明申请
    HIGH SPEED MEASUREMENT OF RANDOM VARIATION/YIELD IN INTEGRATED CIRCUIT DEVICE TESTING 失效
    集成电路设备测试中随机变化/线性的高速度测量

    公开(公告)号：US20110169499A1

    公开(公告)日：2011-07-14

    申请号：US12686476

    申请日：2010-01-13

    申请人： Manjul Bhushan ,  Mark B. Ketchen ,  Qingqing Liang ,  Edward P. Maciejewski

    发明人： Manjul Bhushan ,  Mark B. Ketchen ,  Qingqing Liang ,  Edward P. Maciejewski

    IPC分类号： G01R31/02 ,  G01R19/00

    CPC分类号： G01R31/2856 ,  G01R31/2894

    摘要： A test structure is provided that utilizes a time division sampling technique along with a statistical modeling technique that uses metal-oxide-semiconductor field effect transistor (MOSFET) saturation and linear characteristics to measure the mean (average) and sigma (statistical characterization of the variation) of a large population of electrical characteristics of electrical devices (e.g., integrated circuits) at high speed. Such electrical characteristics or sampling parameters include drive currents, leakage, resistances, etc.

    摘要翻译： 提供了一种测试结构，其利用时分采样技术以及使用金属氧化物半导体场效应晶体管（MOSFET）饱和度和线性特性的统计建模技术来测量平均值（平均）和σ（变化的统计特征） ）高速电气设备（如集成电路）的大量电气特性。 这种电气特性或采样参数包括驱动电流，泄漏，电阻等

    ACQUISITION OF SILICON-ON-INSULATOR SWITCHING HISTORY EFFECTS STATISTICS
    2.
    发明申请
    ACQUISITION OF SILICON-ON-INSULATOR SWITCHING HISTORY EFFECTS STATISTICS 失效
    绝缘体绝缘体开关历史效应统计资料

    公开(公告)号：US20110043242A1

    公开(公告)日：2011-02-24

    申请号：US12544772

    申请日：2009-08-20

    申请人： Manjul Bhushan ,  Mark B. Ketchen

    发明人： Manjul Bhushan ,  Mark B. Ketchen

    IPC分类号： G01R31/26 ,  G01R31/02

    CPC分类号： G01R31/31725 ,  G01R31/31727

    摘要： A test structure for gathering switching history effect statistics includes a waveform generator circuit that selectively generates a first test waveform representative of a 1SW transistor switching event, and a second test waveform representative of a 2SW transistor switching event; and a history element circuit coupled to the waveform generator circuit, the history element circuit including a device under test (DUT) therein, and a variable delay chain therein, wherein a selected one of the first and second test waveforms are input to the DUT and the variable delay chain; wherein the history element circuit determines fractional a change in signal propagation delay through the DUT between the 1SW and 2SW transistor switching events, with the fractional change in signal propagation delay calibrated with timing measurements of a variable frequency ring oscillator; and wherein the test structure utilizes only external low-speed input and output signals with respect to a chip.

    摘要翻译： 用于采集切换历史效果统计的测试结构包括：选择性地产生代表1SW晶体管切换事件的第一测试波形的波形发生器电路和代表2SW晶体管切换事件的第二测试波形; 以及耦合到所述波形发生器电路的历史元件电路，所述历史元件电路包括其中的被测器件（DUT）及其中的可变延迟链，其中所述第一和第二测试波形中的所选择的一个输入到所述DUT， 可变延迟链; 其中历史元件电路通过在1SW和2SW晶体管切换事件之间通过DUT的信号传播延迟的变化来确定分数，其中通过可变频率环形振荡器的定时测量校准信号传播延迟的分数变化; 并且其中测试结构仅利用相对于芯片的外部低速输入和输出信号。

    Methods and Apparatus for Inline Variability Measurement of Integrated Circuit Components
    4.
    发明申请
    Methods and Apparatus for Inline Variability Measurement of Integrated Circuit Components 失效
    集成电路元件在线可变性测量方法与装置

    公开(公告)号：US20080142848A1

    公开(公告)日：2008-06-19

    申请号：US12041388

    申请日：2008-03-03

    申请人： Manjul Bhushan ,  Karen M.G.V. Gettings ,  Wilfried E. Haensch ,  Brian L. Ji ,  Mark B. Ketchen

    发明人： Manjul Bhushan ,  Karen M.G.V. Gettings ,  Wilfried E. Haensch ,  Brian L. Ji ,  Mark B. Ketchen

    IPC分类号： H01L27/088

    CPC分类号： G01R31/2884 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit device is provided including at least one first array configuration of integrated circuit components comprising a m×n array of FETs, without specified internal connections between the integrated circuit components, wherein m is greater than two. The integrated circuit device further includes at least one second array configuration of integrated circuit components comprising an array of integrated circuit components nominally identical to those of the first array configuration, with specified internal connections between integrated circuit components. A variation coefficient is determined for the integrated circuit components based on a measured specified parameter of the first array configuration and the second array configuration.

    摘要翻译： 提供一种集成电路器件，其包括至少一个集成电路部件的第一阵列结构，该集成电路部件包括一组FET，该集成电路阵列在集成电路部件之间没有规定的内部连接，其中m大于2。 集成电路装置还包括集成电路部件的至少一个第二阵列配置，其包括与第一阵列配置的名义上相同的集成电路组件的阵列，以及集成电路部件之间的指定的内部连接。 基于第一阵列配置和第二阵列配置的测量的指定参数来确定集成电路组件的变化系数。

    Measurement of partially depleted silicon-on-insulator CMOS circuit leakage current under different steady state switching conditions
    5.
    发明授权
    Measurement of partially depleted silicon-on-insulator CMOS circuit leakage current under different steady state switching conditions 失效
    在不同的稳态切换条件下测量部分耗尽的绝缘体上硅绝缘体CMOS电路漏电流

    公开(公告)号：US08310269B2

    公开(公告)日：2012-11-13

    申请号：US12544730

    申请日：2009-08-20

    申请人： Manjul Bhushan ,  Mark B. Ketchen

    发明人： Manjul Bhushan ,  Mark B. Ketchen

    IPC分类号： G01R31/26 ,  G01R31/3187

    CPC分类号： G01R31/2621 ,  G01R31/3008

    摘要： A test system for determining leakage of an integrated circuit (IC) under test includes a test circuit formed on a same chip as the IC, the test circuit further having pulse generator configured to generate a high-speed input signal to the IC at a plurality of selectively programmable duty cycles and frequencies, the IC powered from a first power source independent from a second power source that powers the pulse generator; and a current measuring device configured to measure leakage current through the IC in a quiescent state, and current through the IC in an active switching state, responsive to the high-speed input signal at a plurality of the programmable duty cycles and frequencies, and wherein the test circuit utilizes only external low-speed input and output signals with respect to the chip.

    摘要翻译： 一种用于确定被测集成电路（IC）的泄漏的测试系统，包括与IC相同的芯片上形成的测试电路，该测试电路还具有脉冲发生器，该脉冲发生器被配置成以多个产生IC的高速输入信号 有选择地可编程占空比和频率，所述IC由独立于所述脉冲发生器供电的第二电源的第一电源供电; 以及电流测量装置，其被配置为响应于多个可编程占空比和频率的高速输入信号来测量处于静止状态的通过IC的泄漏电流和通过IC的处于主动切换状态的电流，并且其中 测试电路仅使用相对于芯片的外部低速输入和输出信号。

    MEASUREMENT OF PARTIALLY DEPLETED SILICON-ON-INSULATOR CMOS CIRCUIT LEAKAGE CURRENT UNDER DIFFERENT STEADY STATE SWITCHING CONDITIONS
    6.
    发明申请
    MEASUREMENT OF PARTIALLY DEPLETED SILICON-ON-INSULATOR CMOS CIRCUIT LEAKAGE CURRENT UNDER DIFFERENT STEADY STATE SWITCHING CONDITIONS 失效
    在不同的稳态切换条件下测量部分绝缘的绝缘体上的CMOS电路漏电流

    公开(公告)号：US20110043243A1

    公开(公告)日：2011-02-24

    申请号：US12544730

    申请日：2009-08-20

    申请人： Manjul Bhushan ,  Mark B. Ketchen

    发明人： Manjul Bhushan ,  Mark B. Ketchen

    IPC分类号： G01R31/26 ,  G01R31/02

    CPC分类号： G01R31/2621 ,  G01R31/3008

    摘要： A test system for determining leakage of an integrated circuit (IC) under test includes a test circuit formed on a same chip as the IC, the test circuit further having pulse generator configured to generate a high-speed input signal to the IC at a plurality of selectively programmable duty cycles and frequencies, the IC powered from a first power source independent from a second power source that powers the pulse generator; and a current measuring device configured to measure leakage current through the IC in a quiescent state, and current through the IC in an active switching state, responsive to the high-speed input signal at a plurality of the programmable duty cycles and frequencies, and wherein the test circuit utilizes only external low-speed input and output signals with respect to the chip.

    摘要翻译： 一种用于确定被测集成电路（IC）的泄漏的测试系统，包括与IC相同的芯片上形成的测试电路，该测试电路还具有脉冲发生器，该脉冲发生器被配置成以多个产生IC的高速输入信号 有选择地可编程占空比和频率，所述IC由独立于所述脉冲发生器供电的第二电源的第一电源供电; 以及电流测量装置，其被配置为响应于多个可编程占空比和频率的高速输入信号来测量处于静止状态的通过IC的泄漏电流和通过IC的处于主动切换状态的电流，并且其中 测试电路仅使用相对于芯片的外部低速输入和输出信号。

    SINGLE LEVEL OF METAL TEST STRUCTURE FOR DIFFERENTIAL TIMING AND VARIABILITY MEASUREMENTS OF INTEGRATED CIRCUITS
    7.
    发明申请
    SINGLE LEVEL OF METAL TEST STRUCTURE FOR DIFFERENTIAL TIMING AND VARIABILITY MEASUREMENTS OF INTEGRATED CIRCUITS 失效
    金属测试结构的单一级别，用于差分时序和集成电路的可变性测量

    公开(公告)号：US20110043215A1

    公开(公告)日：2011-02-24

    申请号：US12544750

    申请日：2009-08-20

    申请人： Manjul Bhushan ,  Mark B. Ketchen ,  Chin Kim

    发明人： Manjul Bhushan ,  Mark B. Ketchen ,  Chin Kim

    IPC分类号： G01R31/02

    CPC分类号： G01R31/31725 ,  G01R31/3016

    摘要： A test structure for an integrated circuit device includes one or more experiments selectively configured to receive one or more high-speed input signals as inputs thereto and to output at least one high-speed output signal therefrom, the one or more experiments each comprising two or more logic gates configured to determine differential delay characteristics of individual circuit devices, at a precision level on the order of picoseconds to less than 1 picosecond; and wherein the one or more sets of experiments are disposed, and are fully testable, at a first level of metal wiring (M1) in the integrated circuit device.

    摘要翻译： 用于集成电路装置的测试结构包括一个或多个实验，其被选择性地配置为接收一个或多个高速输入信号作为其输入并从其输出至少一个高速输出信号，所述一个或多个实验各自包括两个或多个 多个逻辑门被配置为确定各个电路装置的差分延迟特性，其精度水平以皮秒级小于1皮秒; 并且其中所述一组或多组实验在所述集成电路装置中的金属布线（M1）的第一级处被布置并且是完全可测试的。

    Methods and Apparatus for Determining a Switching History Time Constant in an Integrated Circuit Device
    8.
    发明申请
    Methods and Apparatus for Determining a Switching History Time Constant in an Integrated Circuit Device 有权
    用于确定集成电路器件中的开关历史时间常数的方法和装置

    公开(公告)号：US20090271134A1

    公开(公告)日：2009-10-29

    申请号：US12110639

    申请日：2008-04-28

    申请人： Manjul Bhushan ,  Mark B. Ketchen ,  Dale J. Pearson

    发明人： Manjul Bhushan ,  Mark B. Ketchen ,  Dale J. Pearson

    IPC分类号： G01R29/00

    CPC分类号： G01R31/31707 ,  G01R31/3016 ,  G01R31/31708 ,  H03K5/04

    摘要： Techniques for inline measurement of a switching history time constant in an integrated circuit device are provided. A series of pulses is launched into a first stage of a delay chain comprising a plurality of delay stages connected in series and having a length greater than a decay length of at least an initial one of the series of pulses, such that the at least initial one of the series of pulses does not appear at a second stage of the delay chain. An amount of time between the launching of the initial one of the series of pulses and the appearance of at least one of the series of pulses at the second stage of the delay chain is determined. The switching history time constant is calculated as a function of a number of stages traversed by the at least one pulse, the determined amount of time, and the decay length of the at least initial one of the series of pulses based at least in part on a switching history of the integrated circuit device.

    摘要翻译： 提供了用于集成电路装置中的切换历史时间常数的在线测量的技术。 一系列脉冲被发射到延迟链的第一级中，该延迟链包括多个串联连接的延迟级，其长度大于该系列脉冲中的至少初始脉冲的衰减长度，使得至少初始 一系列脉冲之一不出现在延迟链的第二阶段。 确定在延迟链的第二阶段发射一系列脉冲中的初始脉冲之一和至少一个脉冲串的出现之间的时间量。 切换历史时间常数被计算为至少部分地基于至少一个脉冲遍历的次数的数量，所确定的时间量以及该系列脉冲中的至少初始脉冲的衰减长度的函数 集成电路装置的切换历史。

    Methods and apparatus for inline variability measurement of integrated circuit components
    9.
    发明授权
    Methods and apparatus for inline variability measurement of integrated circuit components 有权
    集成电路元件在线可变性测量方法与装置

    公开(公告)号：US07342406B2

    公开(公告)日：2008-03-11

    申请号：US11297730

    申请日：2005-12-08

    申请人： Manjul Bhushan ,  Karen M. G. V. Gettings ,  Wilfried E. Haensch ,  Brian L. Ji ,  Mark B. Ketchen

    发明人： Manjul Bhushan ,  Karen M. G. V. Gettings ,  Wilfried E. Haensch ,  Brian L. Ji ,  Mark B. Ketchen

    IPC分类号： G01R31/26

    CPC分类号： G01R31/2884 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of measuring variability of integrated circuit components is provided. A specified parameter of at least one first array configuration comprising a plurality of the integrated circuit components without specified internal connections between the integrated circuit components is measured. The specified parameter of at least one second array configuration comprising a plurality of the integrated circuit components nominally identical to those of the first array configuration with specified internal connections between the integrated circuit components is also measured. A variation coefficient is determined for the integrated circuit components based on the measured specified parameter of the at least one first array configuration and the at least one second array configuration.

    摘要翻译： 提供了一种测量集成电路部件的可变性的方法。 测量包括集成电路部件之间没有规定内部连接的多个集成电路部件的至少一个第一阵列配置的指定参数。 还测量包括与集成电路部件之间具有规定的内部连接的第一阵列配置的名义上相同的多个集成电路部件的至少一个第二阵列配置的指定参数。 基于所测量的至少一个第一阵列配置和至少一个第二阵列配置的指定参数，为集成电路组件确定变化系数。