公开(公告)号：US06707325B2

公开(公告)日：2004-03-16

申请号：US10278080

申请日：2002-10-23

Applicant: Masao Taguchi ,  Satoshi Eto ,  Yoshihiro Takemae ,  Hiroshi Yoshioka ,  Makoto Koga

Inventor： Masao Taguchi ,  Satoshi Eto ,  Yoshihiro Takemae ,  Hiroshi Yoshioka ,  Makoto Koga

IPC: H03K300

CPC classification number: H03K19/018585

Abstract: A semiconductor integrated circuit includes a switch unit for controlling the supply of a power source voltage to a signal amplification circuit for receiving an input signal, and a control unit for selectively turning ON and OFF the switch unit in accordance with the amplitude or frequency of the input signal. By the constitution, it is possible to provide an input circuit or an output circuit capable of being applied to an input/output interface adapted for a small amplitude operation.

公开(公告)号：US5936897A

公开(公告)日：1999-08-10

申请号：US48996

申请日：1998-03-27

Applicant: Makoto Koga

Inventor： Makoto Koga

IPC: G11C11/409 ,  G11C7/06 ,  G11C7/10 ,  G11C7/22 ,  G11C16/06 ,  G11C7/00

CPC classification number: G11C7/1048 ,  G11C7/065 ,  G11C7/22

Abstract: The present invention relates to a memory device including a sense amplifier for driving bit line pair and write amplifier for driving data bus line connecting to the bit line pair. According to the present invention, when the column gates are opened and the sense amplifiers are connected to the data bus amplifiers via the data bus pair, one sense amplifier circuit portion of each sense amplifier is deactivated and the conflicts which arise from the operation of the write amplifiers in the data bus amplifiers and of the sense amplifiers can be avoided, and the writing operation can be performed at a high speed. In addition, the control of the sense amplifiers need not be changed either for the reading process or for the writing process, and the writing speed can be increased without the reading being affected.

Abstract translation: 本发明涉及包括用于驱动位线对的读出放大器和用于驱动连接到位线对的数据总线的写放大器的存储器件。 根据本发明，当列门打开并且读出放大器经由数据总线对连接到数据总线放大器时，每个读出放大器的一个读出放大器电路部分被去激活，并且由于操作引起的冲突 可以避免数据总线放大器和读出放大器中的写放大器，并且可以高速执行写入操作。 此外，对于读取处理或写入处理，读出放大器的控制不需要改变，并且可以在不影响读取的情况下增加写入速度。

公开(公告)号：US06936889B2

公开(公告)日：2005-08-30

申请号：US10824474

申请日：2004-04-15

Applicant: Makoto Koga ,  Kunihiko Gotoh ,  Kenichi Matsumaru ,  Mitsuya Kawata

Inventor： Makoto Koga ,  Kunihiko Gotoh ,  Kenichi Matsumaru ,  Mitsuya Kawata

IPC: G01R31/28 ,  G11C8/12 ,  G11C29/12 ,  G11C29/26 ,  G11C29/56 ,  G11C5/02

CPC classification number: G11C29/26 ,  G11C8/12

Abstract: A semiconductor device having at least three independently accessible memories, with at least one of the memories having a different memory capacity than the others. Separate selection signals are provided to the memories so that they can be independently activated. This allows the memories to be separately tested. When testing the semiconductor device, the memories are tested serially, except for the memory with the largest capacity, since this memory also has the longest test time. The memory with the longest test time is tested in parallel with the serially tested memories. This reduces the current that must be supplied by a test device to the semiconductor device during testing.

Abstract translation: 具有至少三个可独立存取存储器的半导体器件，其中至少一个存储器具有与其它存储器不同的存储器容量。 将独立的选择信号提供给存储器，使得它们可以被独立地激活。 这允许记忆分开测试。 当测试半导体器件时，除了具有最大容量的存储器之外，连续测试存储器，因为该存储器也具有最长的测试时间。 具有最长测试时间的存储器与串行测试的存储器并行测试。 这在测试期间将测试装置必须提供的电流减少到半导体器件。

公开(公告)号：US06373414B1

公开(公告)日：2002-04-16

申请号：US09947503

申请日：2001-09-07

Applicant: Makoto Koga ,  Yoshinori Okajima

Inventor： Makoto Koga ,  Yoshinori Okajima

IPC: H03M900

Abstract: According to the present invention, a serial/parallel converter, which outputs, with the same phase and in parallel, a plurality of data sets input serially in synchronization with an input clock, comprises: at least two input latch flip-flops for latching the plurality of input data sets in synchronization with the input clock; a pulse generator for generating a plurality of latch clocks synchronously with timings at which the plurality of data sets are held by the input latch flip-flops; a plurality of holding flip-flips for latching in order the plurality of data sets held by the input latch flip-flops in accordance with the plurality of latch clocks; and a plurality of output latch flip-flops for, in accordance with the last latch clock synchronous with when the last data set of the plurality of data sets is held by the input latch flip-flops, latching in parallel the plurality of data sets held by the holding flip-flops and the last data set by the input latch flip-flops.

公开(公告)号：US06528817B1

公开(公告)日：2003-03-04

申请号：US09626107

申请日：2000-07-26

Applicant: Makoto Koga ,  Kunihiko Gotoh ,  Kenichi Matsumaru ,  Mitsuya Kawata

Inventor： Makoto Koga ,  Kunihiko Gotoh ,  Kenichi Matsumaru ,  Mitsuya Kawata

IPC: H01L2900

CPC classification number: G11C29/26 ,  G11C8/12

Abstract: A semiconductor device having at least three independently accessible memories, with at least one of the memories having a different memory capacity than the others. Separate selection signals are provided to the memories so that they can be independently activated. This allows the memories to be separately tested. When testing the semiconductor device, the memories are tested serially, except for the memory with the largest capacity, since this memory also has the longest test time. The memory with the longest test time is tested in parallel with the serially tested memories. This reduces the current that must be supplied by a test device to the semiconductor device during testing.

Abstract translation: 具有至少三个可独立存取存储器的半导体器件，其中至少一个存储器具有与其它存储器不同的存储器容量。 将独立的选择信号提供给存储器，使得它们可以被独立地激活。 这允许记忆分开测试。 当测试半导体器件时，除了具有最大容量的存储器之外，连续测试存储器，因为该存储器也具有最长的测试时间。 具有最长测试时间的存储器与串行测试的存储器并行测试。 这在测试期间将测试装置必须提供的电流减少到半导体器件。

公开(公告)号：US06339387B1

公开(公告)日：2002-01-15

申请号：US09583232

申请日：2000-05-31

Applicant: Makoto Koga

Inventor： Makoto Koga

IPC: H03M900

CPC classification number: H03M9/00

Abstract: According to the present invention, a serial/parallel converter, which outputs, with the same phase and in parallel, a plurality of data sets input serially in synchronization with an input clock, comprises: at least two input latch flip-flops for latching the plurality of input data sets in synchronization with the input clock; a pulse generator for generating a plurality of latch clocks synchronously with timings at which the plurality of data sets are held by the input latch flip-flops; a plurality of holding flip-flips for latching in order the plurality of data sets held by the input latch flip-flops in accordance with the plurality of latch clocks; and a plurality of output latch flip-flops for, in accordance with the last latch clock synchronous with when the last data set of the plurality of data sets is held by the input latch flip-flops, latching in parallel the plurality of data sets held by the holding flip-flops and the last data set by the input latch flip-flops.

公开(公告)号：US6119150A

公开(公告)日：2000-09-12

申请号：US789184

申请日：1997-01-24

Applicant: Hiroaki Fujii ,  Tadaaki Isobe ,  Makoto Koga ,  Hideya Akashi

Inventor： Hiroaki Fujii ,  Tadaaki Isobe ,  Makoto Koga ,  Hideya Akashi

IPC: G06F15/17 ,  G06F12/08 ,  G06F15/167 ,  G06F13/00

CPC classification number: G06F12/0837 ,  G06F12/0813

Abstract: An instruction processor is employed which performs a cache coherence control according to a request from the storage controller. The storage controller is provided with a cache coherence control processing circuit, which performs the cache coherence control for the addresses which are the destinations of main memory accesses occurring with a data transfer. At the same time, the cache coherence control processing circuit performs the cache coherence control processing once for each cache line in the process of data transfer. The cache coherence control processing performed by software in connection with data transfer is obviated, improving the data transfer efficiency including the cache memory control and reducing limitations on program.

Abstract translation: 采用根据来自存储控制器的请求执行高速缓存一致性控制的指令处理器。 存储控制器设置有高速缓存一致性控制处理电路，其对作为通过数据传送发生的主存储器访问的目的地的地址执行高速缓存一致性控制。 同时，高速缓存一致性控制处理电路在数据传送过程中对每条高速缓存线执行一次高速缓存一致性控制处理。 消除了与数据传输有关的软件执行的高速缓存一致性控制处理，提高了包括缓存存储器控制在内的数据传输效率，并减少了对程序的限制。

公开(公告)号：US5557221A

公开(公告)日：1996-09-17

申请号：US76434

申请日：1993-06-14

Applicant: Masao Taguchi ,  Satoshi Eto ,  Yoshihiro Takemae ,  Hiroshi Yoshioka ,  Makoto Koga

Inventor： Masao Taguchi ,  Satoshi Eto ,  Yoshihiro Takemae ,  Hiroshi Yoshioka ,  Makoto Koga

IPC: H03K19/0185 ,  H03F3/45

CPC classification number: H03K19/018585

Abstract: A semiconductor integrated circuit includes a switch unit for controlling the supply of a power source voltage to a signal amplification circuit for receiving an input signal, and a control unit for selectively turning ON and OFF the switch unit in accordance with the amplitude or frequency of this input signal. By the constitution, it is possible to provide an input circuit or an output circuit capable of being applied to an input/output interface adapted for a small amplitude operation.

Abstract translation: 半导体集成电路包括用于控制向接收输入信号的信号放大电路提供电源电压的开关单元，以及根据该开关单元的幅度或频率选择性地接通和断开开关单元的控制单元 输入信号。 通过该结构，可以提供能够应用于适于小振幅操作的输入/输出接口的输入电路或输出电路。

公开(公告)号：US07639038B2

公开(公告)日：2009-12-29

申请号：US11485396

申请日：2006-07-13

Applicant: Yutaka Nemoto ,  Yoshimasa Ogawa ,  Miki Yanagawa ,  Makoto Koga

Inventor： Yutaka Nemoto ,  Yoshimasa Ogawa ,  Miki Yanagawa ,  Makoto Koga

IPC: H03K17/16 ,  H03K19/003

CPC classification number: H04L25/0298

Abstract: A terminal resistance adjusting method adjusts a terminating resistance within a semiconductor integrated circuit. The method includes obtaining a comparison result by comparing a reference voltage and a voltage of a first node that is coupled to a first voltage via a current supply circuit, the first voltage being one of a power supply voltage and a ground voltage, controlling a monitoring resistor part which has a plurality of first resistors when making a calibration, so as to selectively couple the first resistors in parallel between the first node and a second voltage based on the comparison result, the second voltage being the other of the power supply voltage and the ground voltage, and controlling a terminating resistor part which has a plurality of second resistors when controlling the terminating resistance of the terminating part, so as to selectively couple the second resistors in parallel between a second node and the second voltage based on the comparison result similarly to the first resistors of the monitoring resistor part.

Abstract translation: 终端电阻调整方法调整半导体集成电路内的终端电阻。 该方法包括通过比较经由电流供应电路耦合到第一电压的第一节点的参考电压和电压，第一电压是电源电压和接地电压之一来获得比较结果，控制监视 电阻部分，当进行校准时具有多个第一电阻器，以便基于比较结果选择性地将第一电阻并联在第一节点和第二电压之间，第二电压是电源电压的另一个， 接地电压，并且当控制终端部分的终止电阻时控制具有多个第二电阻器的终端电阻器部分，以便基于比较结果选择性地将第二电阻并联连接在第二节点和第二电压之间 类似于监控电阻器部分的第一个电阻。

公开(公告)号：US06740929B2

公开(公告)日：2004-05-25

申请号：US10320420

申请日：2002-12-17

Applicant: Makoto Koga ,  Kunihiko Gotoh ,  Kenichi Matsumaru ,  Mitsuya Kawata

Inventor： Makoto Koga ,  Kunihiko Gotoh ,  Kenichi Matsumaru ,  Mitsuya Kawata

IPC: H01L2900

CPC classification number: G11C29/26 ,  G11C8/12

Abstract: A semiconductor device having at least three independently accessible memories, with at least one of the memories having a different memory capacity than the others. Separate selection signals are provided to the memories so that they can be independently activated. This allows the memories to be separately tested. When testing the semiconductor device, the memories are tested serially, except for the memory with the largest capacity, since this memory also has the longest test time. The memory with the longest test time is tested in parallel with the serially tested memories. This reduces the current that must be supplied by a test device to the semiconductor device during testing.

Abstract translation: 具有至少三个可独立存取存储器的半导体器件，其中至少一个存储器具有与其它存储器不同的存储器容量。 将独立的选择信号提供给存储器，使得它们可以被独立地激活。 这允许记忆分开测试。 当测试半导体器件时，除了具有最大容量的存储器之外，连续测试存储器，因为该存储器也具有最长的测试时间。 具有最长测试时间的存储器与串行测试的存储器并行测试。 这在测试期间将测试装置必须提供的电流减少到半导体器件。