公开(公告)号：US11710688B2

公开(公告)日：2023-07-25

申请号：US17363459

申请日：2021-06-30

Applicant: MEDIATEK INC.

Inventor： Hsing-Chih Liu ,  Zheng Zeng ,  Che-Hung Kuo

IPC: H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H01L23/48 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L23/49811 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/5385 ,  H01L23/5389 ,  H01L25/0657 ,  H01L25/105

Abstract: A semiconductor package structure includes a frontside redistribution layer, a stacking structure, a backside redistribution layer, a first intellectual property (IP) core, and a second IP core. The stacking structure is disposed over the frontside redistribution layer and comprises a first semiconductor die and a second semiconductor die over the first semiconductor die. The backside redistribution layer is disposed over the stacking structure. The first IP core is disposed in the stacking structure and is electrically coupled to the frontside redistribution layer through a first routing channel. The second IP core is disposed in the stacking structure and is electrically coupled to the backside redistribution layer through a second routing channel, wherein the second routing channel is separated from the first routing channel and electrically insulated from the frontside redistribution layer.

公开(公告)号：US20220102297A1

公开(公告)日：2022-03-31

申请号：US17549901

申请日：2021-12-14

Applicant: MEDIATEK INC.

Inventor： Chia-Hao Hsu ,  Tai-Yu Chen ,  Shiann-Tsong Tsai ,  Hsing-Chih Liu ,  Yao-Pang Hsu ,  Chi-Yuan Chen ,  Chung-Fa Lee

IPC: H01L23/66 ,  H01L23/367 ,  H01L23/373 ,  H01L23/498 ,  H01L23/00 ,  H01Q1/02 ,  H01Q1/22

Abstract: A semiconductor package including a base comprising an upper surface and a lower surface that is opposite to the upper surface; a radio-frequency (RF) module embedded near the upper surface of the base; an integrated circuit (IC) die mounted on the lower surface of the base in a flip-chip manner so that a backside of the IC die is available for heat dissipation; a plurality of conductive structures disposed on the lower surface of the base and arranged around the IC die; and a metal thermal interface layer comprising a backside metal layer that is in contact with the backside of the IC die, and a solder paste conformally printed on the backside metal layer.

公开(公告)号：US20200243464A1

公开(公告)日：2020-07-30

申请号：US16802576

申请日：2020-02-27

Applicant: MEDIATEK INC.

Inventor： Chia-Hao Hsu ,  Tai-Yu Chen ,  Shiann-Tsong Tsai ,  Hsing-Chih Liu ,  Yao-Pang Hsu ,  Chi-Yuan Chen ,  Chung-Fa Lee

IPC: H01L23/66 ,  H01Q1/02 ,  H01Q1/22 ,  H01L23/00 ,  H01L23/367 ,  H01L23/498 ,  H01L23/373

Abstract: A semiconductor package includes a base comprising a top surface and a bottom surface that is opposite to the top surface; a first semiconductor chip mounted on the top surface of the base in a flip-chip manner; a second semiconductor chip stacked on the first semiconductor chip and electrically coupled to the base by wire bonding; an in-package heat dissipating element comprising a dummy silicon die adhered onto the second semiconductor chip by using a high-thermal conductive die attach film; and a molding compound encapsulating the first semiconductor die, the second semiconductor die, and the in-package heat dissipating element.

公开(公告)号：US09991227B2

公开(公告)日：2018-06-05

申请号：US15385988

申请日：2016-12-21

Applicant: MediaTek Inc.

Inventor： Hsing-Chih Liu ,  Chia-Hao Yang ,  Ying-Chih Chen

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0655 ,  H01L23/49575 ,  H01L23/50 ,  H01L23/5221 ,  H01L23/528 ,  H01L23/5381 ,  H01L23/5386 ,  H01L24/05 ,  H01L24/06 ,  H01L24/09 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/0612 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48138 ,  H01L2224/48139 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48479 ,  H01L2224/4903 ,  H01L2224/4909 ,  H01L2224/4911 ,  H01L2224/4912 ,  H01L2224/4917 ,  H01L2224/49171 ,  H01L2224/4945 ,  H01L2224/73265 ,  H01L2224/85181 ,  H01L2224/85186 ,  H01L2224/85205 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2224/4554

Abstract: A semiconductor package structure includes a base. A first die is mounted on the base. The first die includes a plurality of first pads arranged in a first tier, and a plurality of second pads arranged in a second tier. A second die is mounted on the base and includes a plurality of third pads with the first pad area, and a plurality of fourth pads with the second pad area, alternately arranged in a third tier. The second die also includes a first bonding wire having two terminals respectively coupled to one of the first pads and one of the fourth pads. The semiconductor package structure also includes a second bonding wire having two terminals respectively coupled to one of the third pads and one of the second pads.

公开(公告)号：US20230307421A1

公开(公告)日：2023-09-28

申请号：US18203631

申请日：2023-05-30

Applicant: MEDIATEK INC.

Inventor： Ta-Jen Yu ,  Wen-Chin Tsai ,  Isabella Song ,  Tai-Yu Chen ,  Che-Hung Kuo ,  Hsing-Chih Liu ,  Shih-Chin Lin ,  Wen-Sung Hsu

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/49816 ,  H01L24/17 ,  H10B80/00

Abstract: A package-on-package includes a first package and a second package on the first package. The first package includes a bottom substrate and a top substrate space apart from the bottom substrate such that the bottom substrate and the top substrate define a gap therebetween. A logic die and an IC device are mounted on the bottom substrate in a side-by-side configuration. The logic die has a thickness not less than 125 micrometer. Copper cored solder balls are disposed between around the logic die and the IC device to electrically connect the bottom substrate with the top substrate. A sealing resin is filled into the gap between the bottom substrate and the top substrate and seals the logic die, the IC device, and the copper cored solder balls in the gap.

公开(公告)号：US11244913B2

公开(公告)日：2022-02-08

申请号：US16699851

申请日：2019-12-02

Applicant: MEDIATEK Inc.

Inventor： Ying-Chih Chen ,  Yen-Ju Lu ,  Che-Ya Chou ,  Hsing-Chih Liu

IPC: H01L23/66 ,  H01L23/31 ,  H01L23/528 ,  H01L23/532 ,  H01Q1/22

Abstract: A semiconductor package includes a substrate, an electronic component, a dielectric layer a transmitting antenna, a receiving antenna and a FSS (Frequency selective surface) antenna. The electronic component is disposed on and electrically connected with the substrate. The dielectric layer has a dielectric upper surface. The transmitting antenna and the receiving antenna are formed adjacent to the substrate. The FSS antenna is formed adjacent to the dielectric upper surface of the dielectric layer. The FSS antenna is separated from the substrate by the dielectric layer in a wireless signal emitting direction.

公开(公告)号：US11227846B2

公开(公告)日：2022-01-18

申请号：US16742850

申请日：2020-01-14

Applicant: MEDIATEK INC.

Inventor： Chia-Hao Hsu ,  Tai-Yu Chen ,  Shiann-Tsong Tsai ,  Hsing-Chih Liu ,  Yao-Pang Hsu ,  Chi-Yuan Chen ,  Chung-Fa Lee

IPC: H01L27/14 ,  H01L23/66 ,  H01L23/367 ,  H01L23/373 ,  H01L23/498 ,  H01L23/00 ,  H01Q1/02 ,  H01Q1/22

Abstract: A semiconductor package includes a base having an upper surface and a lower surface opposite to the upper surface. An antenna array structure is embedded at the upper surface of the base. An IC die is mounted on the lower surface of the base in a flip-chip manner so that a backside of the IC die is available for heat dissipation. Solder ball pads are disposed on the lower surface of the base and arranged around the IC die. The semiconductor package further includes a metal thermal interface layer having a backside metal layer that is in direct contact with the backside of the IC die, and a solder paste conformally printed on the backside metal layer.

公开(公告)号：US20200303806A1

公开(公告)日：2020-09-24

申请号：US16867583

申请日：2020-05-06

Applicant: MEDIATEK INC.

Inventor： Wen-Chou Wu ,  Yi-Chieh Lin ,  Chia-Yu Jin ,  Hsing-Chih Liu

IPC: H01Q1/22 ,  H01L23/498 ,  H01L25/16 ,  H01Q21/06

Abstract: A semiconductor package includes a bottom chip package having a first side and a second side opposing the first side. The bottom chip package comprises a first semiconductor chip and a second semiconductor chip arranged in a side-by-side manner on the second side. A top antenna package is mounted on the first side of the bottom chip package. The top antenna package comprises a radiative antenna element. A connector is disposed on the second side.

公开(公告)号：US20200243462A1

公开(公告)日：2020-07-30

申请号：US16742850

申请日：2020-01-14

Applicant: MEDIATEK INC.

Inventor： Chia-Hao Hsu ,  Tai-Yu Chen ,  Shiann-Tsong Tsai ,  Hsing-Chih Liu ,  Yao-Pang Hsu ,  Chi-Yuan Chen ,  Chung-Fa Lee

IPC: H01L23/66 ,  H01L23/367 ,  H01L23/373 ,  H01L23/498 ,  H01L23/00 ,  H01Q1/22 ,  H01Q1/02

Abstract: A semiconductor package includes a base having an upper surface and a lower surface opposite to the upper surface. An antenna array structure is embedded at the upper surface of the base. An IC die is mounted on the lower surface of the base in a flip-chip manner so that a backside of the IC die is available for heat dissipation. Solder ball pads are disposed on the lower surface of the base and arranged around the IC die. The semiconductor package further includes a metal thermal interface layer having a backside metal layer that is in direct contact with the backside of the IC die, and a solder paste conformally printed on the backside metal layer.

公开(公告)号：US09564395B2

公开(公告)日：2017-02-07

申请号：US14809482

申请日：2015-07-27

Applicant: MediaTek Inc.

Inventor： Hsing-Chih Liu ,  Chia-Hao Yang ,  Ying-Chih Chen

IPC: H01L23/48 ,  H01L23/522 ,  H01L23/538 ,  H01L23/528 ,  H01L23/50 ,  H01L23/495 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L25/0655 ,  H01L23/49575 ,  H01L23/50 ,  H01L23/5221 ,  H01L23/528 ,  H01L23/5381 ,  H01L23/5386 ,  H01L24/05 ,  H01L24/06 ,  H01L24/09 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/0612 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48138 ,  H01L2224/48139 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48479 ,  H01L2224/4903 ,  H01L2224/4909 ,  H01L2224/4911 ,  H01L2224/4912 ,  H01L2224/4917 ,  H01L2224/49171 ,  H01L2224/4945 ,  H01L2224/73265 ,  H01L2224/85181 ,  H01L2224/85186 ,  H01L2224/85205 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2224/4554

Abstract: A semiconductor package structure includes a base. A first die is mounted on the base. The first die comprises a plurality of first pads with a first pad area arranged in a first tier. A plurality of second pads with a second pad area is arranged in a second tier. A second die is mounted on the base. The second die includes a plurality of third pads arranged in a third tier. A first bonding wire has two terminals respectively coupled to one of the first pads and one of the third pads. A second bonding wire has two terminals respectively coupled to one of the third pads and one of the second pads.

Abstract translation: 半导体封装结构包括基底。 第一个模具安装在基座上。 第一管芯包括多个第一焊盘，第一焊盘区域布置在第一层中。 具有第二焊盘区域的多个第二焊盘被布置在第二层中。 第二个模具安装在基座上。 第二管芯包括布置在第三层中的多个第三焊盘。 第一接合线具有分别耦合到第一焊盘之一和第三焊盘中的一个的两个端子。 第二接合线具有分别耦合到第三焊盘之一和第二焊盘之一的两个端子。