公开(公告)号：US06693825B1

公开(公告)日：2004-02-17

申请号：US10349685

申请日：2003-01-23

Applicant: Manish Sharma ,  Thomas C. Anthony ,  Lung T. Tran

Inventor： Manish Sharma ,  Thomas C. Anthony ,  Lung T. Tran

IPC: G11C1100

CPC classification number: G11C11/15 ,  G11C11/5607 ,  G11C2213/71

Abstract: A memory cell includes a conductor clad with ferromagnetic material; first and second spacer layers on opposite sides of the clad conductor; a first data layer on the first spacer layer; and a second data layer on the second spacer layer.

Abstract translation: 存储单元包括用铁磁材料包覆的导体; 在包层导体的相对侧上的第一和第二间隔层; 第一间隔层上的第一数据层; 以及第二间隔层上的第二数据层。

公开(公告)号：US06483734B1

公开(公告)日：2002-11-19

申请号：US09992426

申请日：2001-11-26

Applicant: Manish Sharma ,  Lung T. Tran

Inventor： Manish Sharma ,  Lung T. Tran

IPC: G11C1702

CPC classification number: H01L27/224 ,  G11C11/005 ,  G11C11/16 ,  G11C11/56 ,  G11C11/5607 ,  G11C11/5671 ,  G11C17/16 ,  G11C2216/26

Abstract: A memory device includes memory cells having a re-writeable element and a write-once element in series with the re-writeable element. The re-writeable element is programmable between a high resistance state and a low resistance state. The write-once element can be an anti-fuse element that is programmable from a high resistance state to a low resistance state, or a fuse element that is programmable from a low resistance state to a high resistance state. The two possible states for the re-writeable element and the two possible states for the write-once element allow the memory cells to store four different bits.

Abstract translation: 存储器件包括具有可重写元件和与可重写元件串联的一次写入元件的存储器单元。 可重写元件可在高电阻状态和低电阻状态之间编程。 一次写入元件可以是可从高电阻状态到低电阻状态的可编程熔丝元件，或可从低电阻状态到高电阻状态的可编程熔丝元件。 可重写元件的两种可能状态和一次写入元件的两种可能状态允许存储单元存储四个不同的位。

公开(公告)号：US06891746B2

公开(公告)日：2005-05-10

申请号：US10351013

申请日：2003-01-25

Applicant: Lung T. Tran ,  Manish Sharma

Inventor： Lung T. Tran ,  Manish Sharma

IPC: G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08 ,  G11C11/14

CPC classification number: G11C11/16

Abstract: A magneto-resistive device includes first and second ferromagnetic layers having different coercivities, and a spacer layer between the first and second layers. Each ferromagnetic layer has a magnetization that can be oriented in either of two directions.

Abstract translation: 磁阻装置包括具有不同矫顽力的第一和第二铁磁层以及第一和第二层之间的间隔层。 每个铁磁层具有可以在两个方向中的任一方向上取向的磁化。

公开(公告)号：US06538920B2

公开(公告)日：2003-03-25

申请号：US09825093

申请日：2001-04-02

Applicant: Manish Sharma ,  Lung T. Tran

Inventor： Manish Sharma ,  Lung T. Tran

IPC: G11C1114

CPC classification number: H01L43/08 ,  B82Y25/00 ,  G11C11/15 ,  G11C11/16 ,  H01F10/3254 ,  H01F10/3268 ,  H01L27/222

Abstract: A magnetic memory cell having read conductor that is wholly clad with a high magnetic permeability soft magnetic material for a pinned-on-the-fly soft ferromagnetic reference layer is disclosed. The magnetic memory cell includes a ferromagnetic data layer, an intermediate layer formed on the ferromagnetic data layer, and a soft ferromagnetic reference layer formed on the intermediate layer. The soft ferromagnetic reference layer includes a read conductor and a ferromagnetic cladding that completely surrounds the read conductor to form a cladded read conductor. The soft ferromagnetic reference layer has a non-pinned orientation of magnetization. When an externally supplied read current flows through the read conductor, the read conductor generates a magnetic field that does not saturate the ferromagnetic cladding and is substantially contained within the ferromagnetic cladding and is operative to dynamically pin the orientation of magnetization in a desired direction. Optionally, the soft ferromagnetic reference layer can include a ferromagnetic cap layer positioned between the ferromagnetic cladding and the intermediate layer and magnetically coupled with the ferromagnetic cladding. A bit of data stored in the ferromagnetic data layer is read by measuring a resistance between the ferromagnetic data layer and the soft ferromagnetic reference layer. The ferromagnetic cladding substantially reduces fringe magnetic fields, reduces the number and complexity of the of layers needed to form a prior pinned reference layer, and reduces a magnitude of the read current sufficient to read the bit of data.

Abstract translation: 公开了一种具有读取导体的磁存储单元，其全部包裹有用于固定在飞行中的软铁磁参考层的高磁导率软磁材料。 磁存储单元包括铁磁数据层，形成在铁磁数据层上的中间层和形成在中间层上的软铁磁参考层。 软铁磁参考层包括完全包围读取导体以形成包层读取导体的读取导体和铁磁包层。 软铁磁参考层具有非固定取向的磁化。 当外部提供的读取电流流过读取导体时，读取导体产生不使铁磁性包层饱和并且基本上包含在铁磁包层内的磁场，并且可操作以在期望的方向上动态地引导磁化取向。 可选地，软铁磁参考层可以包括位于铁磁包层和中间层之间并与铁磁包层磁耦合的铁磁盖层。 通过测量铁磁数据层和软铁磁参考层之间的电阻来读取存储在铁磁数据层中的一些数据。 铁磁包层基本上减少了边缘磁场，减少了形成先前固定参考层所需的层的数量和复杂性，并且减小了足以读取数据位的读取电流的大小。

公开(公告)号：US06473337B1

公开(公告)日：2002-10-29

申请号：US09983404

申请日：2001-10-24

Applicant: Lung T. Tran ,  Manish Sharma ,  Thomas C. Anthony

Inventor： Lung T. Tran ,  Manish Sharma ,  Thomas C. Anthony

IPC: G11C1115

CPC classification number: H01L27/222 ,  G11C11/15

Abstract: A memory device includes dual tunnel junction memory cells having a magnetic tunnel junction in series with a tunnel junction. The magnetic tunnel junction can be changed from a first resistance state to a second resistance state during a write operation. The magnetic tunnel junction can have a differing resistance-voltage characteristic than the tunnel junction, and the differing resistance-voltage characteristics allow the magnetic tunnel junction to be blown without blowing the tunnel junction during a write operation. The change in resistance state of the magnetic tunnel junction changes the resistance of the selected memory cell, which is detectable during a read operation.

Abstract translation: 存储器件包括双隧道结存储器单元，其具有与隧道结串联的磁性隧道结。 在写入操作期间，磁性隧道结可以从第一电阻状态改变到第二电阻状态。 磁性隧道结可以具有与隧道结不同的电阻 - 电压特性，并且不同的电阻 - 电压特性允许磁性隧道结在写入操作期间不会吹动隧道结而被吹动。 磁性隧道结的电阻状态的改变改变了所选择的存储单元的电阻，这在读取操作期间是可检测的。

公开(公告)号：US06885573B2

公开(公告)日：2005-04-26

申请号：US10098206

申请日：2002-03-15

Applicant: Manish Sharma ,  Lung T. Tran

Inventor： Manish Sharma ,  Lung T. Tran

IPC: G11C11/00 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08 ,  G11C17/06

CPC classification number: H01L27/224 ,  G11C11/00 ,  G11C11/15 ,  G11C11/16

Abstract: A data storage device is disclosed that has a plurality of word lines, a plurality of bit lines, and a resistive crosspoint array of memory cells. Each memory cell is connected to a bit line and connected to an isolation diode that further connects to a respective word line. The isolation diode provides a unidirectional conductive path from the bit line to the word line. Each word line provides a common metal-semiconductor contact with each diode sharing the word line such that each diode has a separate metal contact located between the semiconductor portion of the common metal-semiconductor contact and its respective memory cell.

Abstract translation: 公开了一种数据存储装置，其具有多个字线，多个位线和存储器单元的电阻交叉点阵列。 每个存储单元连接到位线并连接到进一步连接到相应字线的隔离二极管。 隔离二极管提供从位线到字线的单向导电路径。 每个字线提供与共享字线的每个二极管共同的金属 - 半导体接触，使得每个二极管具有位于公共金属 - 半导体触点的半导体部分和其相应存储单元之间的单独的金属触点。

公开(公告)号：US06801451B2

公开(公告)日：2004-10-05

申请号：US10235045

申请日：2002-09-03

Applicant: Lung T. Tran ,  Manish Sharma

Inventor： Lung T. Tran ,  Manish Sharma

IPC: G11C1100

CPC classification number: G11C11/5607

Abstract: A memory cell of a data storage device includes serially-connected first and second magnetoresistive devices. The first magnetoresistive device has first and second resistance states. The second magnetoresistive device has third and fourth resistance states. The four resistance states are detectably different.

公开(公告)号：US06577529B1

公开(公告)日：2003-06-10

申请号：US10235011

申请日：2002-09-03

Applicant: Manish Sharma ,  Thomas C. Anthony ,  Lung T. Tran

Inventor： Manish Sharma ,  Thomas C. Anthony ,  Lung T. Tran

IPC: G11C1100

CPC classification number: G11C11/15 ,  G11C11/5607 ,  G11C2213/71

Abstract: A memory cell includes a conductor clad with ferromagnetic material; first and second spacer layers on opposite sides of the clad conductor; a first data layer on the first spacer layer; and a second data layer on the second spacer layer.

Abstract translation: 存储单元包括用铁磁材料包覆的导体; 在包层导体的相对侧上的第一和第二间隔层; 第一间隔层上的第一数据层; 以及第二间隔层上的第二数据层。

公开(公告)号：US06538917B1

公开(公告)日：2003-03-25

申请号：US09963851

申请日：2001-09-25

Applicant: Lung T. Tran ,  Manish Sharma

Inventor： Lung T. Tran ,  Manish Sharma

IPC: G11C1115

CPC classification number: G11C11/16

Abstract: A magneto-resistive device includes data and reference layers having different coercivities. Each layer has a magnetization that can be oriented in either of two directions. The memory device may be read by temporarily setting the magnetization of the reference layer to a known orientation, and determining a resistance state of the device.

Abstract translation: 磁阻装置包括具有不同矫顽力的数据和参考层。 每个层具有可以在两个方向中的任一方向上定向的磁化。 可以通过将参考层的磁化临时设置为已知取向来读取存储器件，并且确定器件的电阻状态。

公开(公告)号：US06434060B1

公开(公告)日：2002-08-13

申请号：US09917882

申请日：2001-07-31

Applicant: Lung T. Tran ,  Manish Sharma

Inventor： Lung T. Tran ,  Manish Sharma

IPC: G11C700

CPC classification number: G11C16/3486 ,  G11C17/16 ,  G11C17/18

Abstract: A method and circuit write a memory cell. The method applies a pulse to a write line connected to the memory cell. The duration of the pulse is not predetermined. The method compares a value on the input side of the cell to a reference value. The method discontinues the pulse on the write line, in response to the comparing step, preferably if the value on the write line exceeds the reference value. The circuit comprises a pulse generator and a comparator. The pulse generator has an output and an enable input. The output is connected to a write line connected to the memory cell. The output, when enabled, carries a pulse. The comparator has two inputs and an output. One of the inputs is connected to the write line. The other of the inputs is connected to a reference. The output is connected to the write line, whereby the pulse is disabled or enabled on the write line depending upon comparator output. A complete memory system comprises an array of memory cells, a write line, and a pulse generator and comparator as described above.

Abstract translation: 一种方法和电路写入一个存储单元。 该方法向连接到存储单元的写入线施加脉冲。 脉冲的持续时间不是预定的。 该方法将单元格输入端的值与参考值进行比较。 该方法响应于比较步骤中止写入线上的脉冲，优选地，如果写入线上的值超过参考值。 电路包括脉冲发生器和比较器。 脉冲发生器具有输出和使能输入。 输出连接到连接到存储单元的写入线。 输出，当使能时，会携带一个脉冲。 比较器有两个输入和一个输出。 其中一个输入连接到写入线。 另一个输入连接到引用。 输出连接到写入线，根据比较器输出，脉冲在写入线上被禁止或使能。 完整的存储器系统包括如上所述的存储器单元阵列，写入线以及脉冲发生器和比较器。