公开(公告)号：US11069553B2

公开(公告)日：2021-07-20

申请号：US15634365

申请日：2017-06-27

Applicant: Lam Research Corporation

Inventor： Alexander Matyushkin ,  John Patrick Holland ,  Harmeet Singh ,  Alexei Marakhtanov ,  Keith Gaff ,  Zhigang Chen ,  Felix Kozakevich

IPC: H01L21/683 ,  H01L21/67

Abstract: A substrate support for a substrate processing system includes a baseplate, a bond layer provided on the baseplate, and a ceramic layer arranged on the bond layer. The ceramic layer includes a first region and a second region located radially outward of the first region, the first region has a first thickness, the second region has a second thickness, and the first thickness is greater than the second thickness.

公开(公告)号：US10585347B2

公开(公告)日：2020-03-10

申请号：US16224651

申请日：2018-12-18

Applicant: Lam Research Corporation

Inventor： Saravanapriyan Sriraman ,  Richard Wise ,  Harmeet Singh ,  Alex Paterson ,  Andrew D. Bailey, III ,  Vahid Vahedi ,  Richard A. Gottscho

IPC: G03F1/36 ,  G06F17/50 ,  G03F1/80 ,  G03F1/70

Abstract: Disclosed are methods of generating a proximity-corrected design layout for photoresist to be used in an etch operation. The methods may include identifying a feature in an initial design layout, and estimating one or more quantities characteristic of an in-feature plasma flux (IFPF) within the feature during the etch operation. The methods may further include estimating a quantity characteristic of an edge placement error (EPE) of the feature by comparing the one or more quantities characteristic of the IFPF to those in a look-up table (LUT, and/or through application of a multivariate model trained on the LUT, e.g., constructed through machine learning methods (MLM)) which associates values of the quantity characteristic of EPE with values of the one or more quantities characteristics of the IFPF. Thereafter, the initial design layout may be modified based on at the determined quantity characteristic of EPE.

公开(公告)号：US20190250501A1

公开(公告)日：2019-08-15

申请号：US16224651

申请日：2018-12-18

Applicant: Lam Research Corporation

Inventor： Saravanapriyan Sriraman ,  Richard Wise ,  Harmeet Singh ,  Alex Paterson ,  Andrew D. Bailey, III ,  Vahid Vahedi ,  Richard A. Gottscho

IPC: G03F1/36 ,  G03F1/80 ,  G03F1/70 ,  G06F17/50

Abstract: Disclosed are methods of generating a proximity-corrected design layout for photoresist to be used in an etch operation. The methods may include identifying a feature in an initial design layout, and estimating one or more quantities characteristic of an in-feature plasma flux (IFPF) within the feature during the etch operation. The methods may further include estimating a quantity characteristic of an edge placement error (EPE) of the feature by comparing the one or more quantities characteristic of the IFPF to those in a look-up table (LUT, and/or through application of a multivariate model trained on the LUT, e.g., constructed through machine learning methods (MLM)) which associates values of the quantity characteristic of EPE with values of the one or more quantities characteristics of the IFPF. Thereafter, the initial design layout may be modified based on at the determined quantity characteristic of EPE.

公开(公告)号：US10217615B2

公开(公告)日：2019-02-26

申请号：US14107641

申请日：2013-12-16

Applicant: Lam Research Corporation

Inventor： Harmeet Singh

IPC: C23C16/50 ,  C23C16/00 ,  C23F1/00 ,  H01J37/32 ,  H01L21/67

Abstract: A plasma processing apparatus for processing semiconductor substrates comprises a plasma processing chamber in which a semiconductor substrate is processed. A process gas source is in fluid communication with the plasma processing chamber and is adapted to supply a process gas into the plasma processing chamber. A RF energy source is adapted to energize the process gas into a plasma state in the plasma processing chamber. Process gas and byproducts of the plasma processing are exhausted from the plasma processing chamber through a vacuum port. At least one component of the plasma processing apparatus comprises a laterally extending optical fiber beneath a plasma exposed surface of the component wherein spatial temperature measurements of the surface are desired to be taken, and a temperature monitoring arrangement coupled to the optical fiber so as to monitor temperatures at different locations along the optical fiber.

公开(公告)号：US20180294140A1

公开(公告)日：2018-10-11

申请号：US16000348

申请日：2018-06-05

Applicant: Lam Research Corporation

Inventor： John C. Valcore, JR. ,  Harmeet Singh ,  Bradford J. Lyndaker

IPC: H01J37/32 ,  H03L7/06 ,  H03L7/00 ,  H03K3/01 ,  H05H1/46

CPC classification number: H01J37/32146 ,  H01J37/32082 ,  H01J37/32174 ,  H01J37/32183 ,  H01J37/3244 ,  H01J37/3255 ,  H01J2237/327 ,  H03K3/01 ,  H03L7/00 ,  H03L7/06 ,  H05H2001/4682

Abstract: A method for achieving sub-pulsing during a state is described. The method includes receiving a clock signal from a clock source, the clock signal having two states and generating a pulsed signal from the clock signal. The pulsed signal has sub-states within one of the states. The sub-states alternate with respect to each other at a frequency greater than a frequency of the states. The method includes providing the pulsed signal to control power of a radio frequency (RF) signal that is generated by an RF generator. The power is controlled to be synchronous with the pulsed signal.

公开(公告)号：US10056225B2

公开(公告)日：2018-08-21

申请号：US14139238

申请日：2013-12-23

Applicant: Lam Research Corporation

Inventor： Keith William Gaff ,  Harmeet Singh ,  Keith Comendant ,  Vahid Vahedi

IPC: C23C16/00 ,  H01J37/20 ,  H01L21/67 ,  H01L21/66

CPC classification number: H01J37/20 ,  H01L21/67248 ,  H01L22/12 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A plasma etching system having a substrate support assembly with multiple independently controllable heater zones. The plasma etching system is configured to control etching temperature of predetermined locations so that pre-etch and/or post-etch non-uniformity of critical device parameters can be compensated for.

公开(公告)号：US20180033596A1

公开(公告)日：2018-02-01

申请号：US15726235

申请日：2017-10-05

Applicant: Lam Research Corporation

Inventor： John C. Valcore, Jr. ,  Harmeet Singh ,  Bradford J. Lyndaker

IPC: H01J37/32 ,  H03K3/01 ,  H03L7/06 ,  H03L7/00 ,  H05H1/46

CPC classification number: H01J37/32146 ,  H01J37/32082 ,  H01J37/32174 ,  H01J37/32183 ,  H01J37/3244 ,  H01J37/3255 ,  H01J2237/327 ,  H03K3/01 ,  H03L7/00 ,  H03L7/06 ,  H05H2001/4682

Abstract: A method for achieving sub-pulsing during a state is described. The method includes receiving a clock signal from a clock source, the clock signal having two states and generating a pulsed signal from the clock signal. The pulsed signal has sub-states within one of the states. The sub-states alternate with respect to each other at a frequency greater than a frequency of the states. The method includes providing the pulsed signal to control power of a radio frequency (RF) signal that is generated by an RF generator. The power is controlled to be synchronous with the pulsed signal.

公开(公告)号：US09484243B2

公开(公告)日：2016-11-01

申请号：US14255730

申请日：2014-04-17

Applicant: Lam Research Corporation

Inventor： Dean J. Larson ,  Jason Augustino ,  Andreas Fischer ,  Andre W. Desepte ,  Harmeet Singh

IPC: H01L21/673 ,  H01L21/687 ,  H01L21/67

CPC classification number: H01L21/68785 ,  H01L21/6719

Abstract: A processing chamber having a chamber housing with a top and sidewalls is provided. The processing chamber has a seal for connecting the sidewalls of the chamber housing to a top of a lower chamber below the processing chamber. A substrate holder is attached to the sidewalls of the chamber housing. Further, a wafer lift ring supported by a side arm extending through the sidewalls has at least three posts each having at least one finger, the top of the fingers defining a first wafer handoff plane. The lower chamber has at least one lowest wafer support that defines a second wafer handoff plane where the height between the first wafer handoff plane and the second wafer handoff plane is not greater than a maximum vertical stroke of a transfer arm that is configured to transfer a wafer from the first wafer handoff plane and the second wafer handoff plane.

Abstract translation: 提供具有具有顶部和侧壁的腔室壳体的处理室。 处理室具有用于将室壳体的侧壁连接到处理室下方的下室的顶部的密封件。 衬底保持器附接到腔室壳体的侧壁。 此外，由侧壁延伸穿过侧壁支撑的晶片提升环具有至少三个柱，每个至少有一个手指，手指的顶部限定第一晶片切换平面。 下室具有限定第二晶片切换平面的至少一个最低的晶片支撑件，其中第一晶片切换平面和第二晶片切换平面之间的高度不大于传输臂的最大垂直冲程，其被配置为传送 晶片从第一晶片切换平面和第二晶片切换平面。

公开(公告)号：US09391267B2

公开(公告)日：2016-07-12

申请号：US14818225

申请日：2015-08-04

Applicant: Lam Research Corporation

Inventor： Meihua Shen ,  Harmeet Singh ,  Samantha S. H. Tan ,  Jeffrey Marks ,  Thorsten Lill ,  Richard P. Janek ,  Wenbing Yang ,  Prithu Sharma

IPC: H01L21/00 ,  H01L43/12 ,  H01L21/02 ,  H01L45/00 ,  H01L27/22 ,  H01L43/02 ,  H01L43/10 ,  C23F4/00

CPC classification number: H01L43/12 ,  C23F1/08 ,  C23F1/12 ,  C23F4/00 ,  H01L21/02554 ,  H01L27/228 ,  H01L43/02 ,  H01L43/10 ,  H01L45/1675

Abstract: A method for etching a stack with at least one metal layer in one or more cycles is provided. An initiation step is preformed, transforming part of the at least one metal layer into metal oxide, metal halide, or lattice damaged metallic sites. A reactive step is performed providing one or more cycles, where each cycle comprises providing an organic solvent vapor to form a solvated metal, metal halide, or metal oxide state and providing an organic ligand solvent to form volatile organometallic compounds.

Abstract translation: 提供一种用于在一个或多个循环中用至少一个金属层蚀刻堆叠的方法。 进行引发步骤，将至少一个金属层的一部分转化为金属氧化物，金属卤化物或晶格损坏的金属部位。 执行反应性步骤提供一个或多个循环，其中每个循环包括提供有机溶剂蒸气以形成溶剂化金属，金属卤化物或金属氧化物状态，并提供有机配体溶剂以形成挥发性有机金属化合物。

公开(公告)号：US20160042921A1

公开(公告)日：2016-02-11

申请号：US14887106

申请日：2015-10-19

Applicant: Lam Research Corporation

Inventor： Rajinder Dhindsa ,  Harmeet Singh

IPC: H01J37/32

CPC classification number: H01J37/32137 ,  H01J37/32082 ,  H01J37/32449 ,  H01J37/32532 ,  H01J37/32623 ,  H01J37/32633 ,  H01J37/32816 ,  H01J37/32834

Abstract: A plasma processing system for processing semiconductor substrates is provided. The plasma processing system includes a plasma processing volume having a volume less than the processing chamber. The plasma processing volume is defined by a top electrode, a substrate support surface opposing the surface of the top electrode and a plasma confinement structure including at least one outlet port. A conductance control structure is movably disposed proximate to the at least one outlet port and capable of controlling an outlet flow through the at least one outlet port between a first flow rate and a second flow rate. The conductance control structure controls the outlet flow rate and an at least one RF source is modulated and at least one process gas flow rate is modulated corresponding to a selected processing state set by the controller during a plasma process.

Abstract translation: 提供一种用于处理半导体衬底的等离子体处理系统 等离子体处理系统包括具有小于处理室的体积的等离子体处理体积。 等离子体处理体积由顶部电极，与顶部电极的表面相对的衬底支撑表面和包括至少一个出口的等离子体约束结构限定。 电导控制结构可移动地设置在靠近所述至少一个出口端口处并且能够控制通过所述至少一个出口端口的出口流在第一流量和第二流量之间。 电导控制结构控制出口流量，并且至少一个RF源被调制，并且至少一个处理气体流量被对应于等离子体处理期间由控制器设置的所选择的处理状态被调制。