公开(公告)号：US20140320730A1

公开(公告)日：2014-10-30

申请号：US14119277

申请日：2011-12-20

Applicant: Kyung-Wook Kim

Inventor： Kyung-Wook Kim

IPC: H04N5/232

CPC classification number: H04N5/23212 ,  G02B7/38 ,  G03B13/36

Abstract: Disclosed is a method for automatically controlling a focal point of a digital optical device, which: performs the steps of a focal point mode for performing a high-speed AF operation, and function processing high-capacity function image data; configures a function mode for detecting function focal point data and comparing it to a critical range; automatically performs switching between the focal point mode and the function mode by using an optical device; yields high-capacity function image data having an adjusted focal point in an environment in which the optical device is used where focal point distances change rapidly when a subject or the user of the optical device is moving; and performs required commands at high speed through the optical device when the user of the storing optical device inputs a required command once.

Abstract translation: 公开了一种自动控制数字光学装置的焦点的方法，该方法包括：执行用于执行高速AF操作的焦点模式和功能处理大容量功能图像数据的步骤; 配置检测功能焦点数据的功能模式，并将其与临界范围进行比较; 通过使用光学装置自动执行焦点模式和功能模式之间的切换; 在光学装置的被摄体或使用者正在移动的情况下，在使用光学装置的焦点距离快速变化的环境中产生具有调节焦点的高容量功能图像数据; 并且当存储光学装置的用户输入所需的命令一次时，通过光学装置高速执行所需的命令。

公开(公告)号：US08482688B2

公开(公告)日：2013-07-09

申请号：US11469974

申请日：2006-09-05

Applicant: Hyuk-Jin Kim ,  Kyung-Wook Kim ,  Dong-Wuuk Seo

Inventor： Hyuk-Jin Kim ,  Kyung-Wook Kim ,  Dong-Wuuk Seo

IPC: G02F1/1343 ,  G02F1/1345 ,  G09G3/18 ,  G09G3/36 ,  H01L29/04 ,  H01L29/10 ,  H01L31/00 ,  H01L27/14 ,  H01L29/15 ,  H01L31/036

CPC classification number: G02F1/13306 ,  G02F1/1345 ,  G02F1/136213 ,  G09G3/3648 ,  G09G2300/0426 ,  G09G2320/0223

Abstract: An array substrate includes a base substrate, a plurality of storage voltage lines, a plurality of connecting lines, and a common voltage applying section. Pixels are formed in regions defined by a plurality of gate lines extending along a first direction and data lines extending along a second direction. The connecting lines are connected to the storage voltage lines that are formed on adjacent pixels of pixels arranged in the second direction. The common voltage applying section applies a common voltage to the storage voltage lines that are formed in a portion of the pixels arranged in the first direction. Thus, a substantially uniform current may be applied to the display area to decrease the distortion of the common voltage, thereby increasing a liquid crystal display device's display quality.

Abstract translation: 阵列基板包括基底基板，多个存储电压线，多个连接线以及公共电压施加部。 像素形成在由沿着第一方向延伸的多个栅极线和沿着第二方向延伸的数据线限定的区域中。 连接线连接到形成在沿第二方向布置的像素的相邻像素上的存储电压线。 公共电压施加部分对形成在沿第一方向布置的像素的一部分中的存储电压线施加公共电压。 因此，可以向显示区域施加大致均匀的电流，以减小公共电压的失真，从而增加液晶显示装置的显示质量。

公开(公告)号：US08373813B2

公开(公告)日：2013-02-12

申请号：US12537348

申请日：2009-08-07

Applicant: Jae-Hyun Park ,  Jong-Hwan Lee ,  Kyung-Wook Kim

Inventor： Jae-Hyun Park ,  Jong-Hwan Lee ,  Kyung-Wook Kim

IPC: G02F1/1333

CPC classification number: G02F1/136204 ,  G02F1/136259 ,  G02F2001/136263

Abstract: An array substrate includes a substrate including a display area and a peripheral area surrounding the display area, data lines disposed in the display area and including a portion thereof extending from the display area into the peripheral area at a first side of a periphery of the display area, and a repair line disposed in the peripheral area and crossing the portion of the data lines extending into the peripheral area. The array substrate also includes a static electricity diode part electrically connected to the repair line and a first data line of the data lines.

Abstract translation: 阵列基板包括具有显示区域和围绕显示区域的外围区域的基板，设置在显示区域中的数据线，并且包括其在显示器的周边的第一侧处从显示区域延伸到周边区域的部分 以及设置在周边区域中并与延伸到周边区域的数据线的部分交叉的修复线。 阵列基板还包括电连接到修复线的静电二极管部分和数据线的第一数据线。

公开(公告)号：US08278723B2

公开(公告)日：2012-10-02

申请号：US12496298

申请日：2009-07-01

Applicant: Kyung-Wook Kim ,  Jong-Hwan Lee ,  Young-Woon Kho ,  Jae-Hyun Park

Inventor： Kyung-Wook Kim ,  Jong-Hwan Lee ,  Young-Woon Kho ,  Jae-Hyun Park

IPC: H01L29/72

CPC classification number: H01L27/1214 ,  H01L27/1288

Abstract: A thin film transistor substrate capable of appropriately maintaining driving performance even when there is a difference between manufacturing processes and a method of manufacturing the same. The thin film transistor substrate includes: a gate electrode formed on an insulating substrate; a semiconductor layer formed on the gate electrode; and a plurality of thin film transistors each having a source electrode and a drain electrode that are formed on the gate electrode and the semiconductor layer so as to be spaced apart from each other. At least one of the plurality of thin film transistors is a dummy thin film transistor that does not have the semiconductor layer between the source electrode and the drain electrode.

Abstract translation: 即使在制造过程之间存在差异的情况下也能够适当地保持驱动性能的薄膜晶体管基板及其制造方法。 薄膜晶体管基板包括：形成在绝缘基板上的栅电极; 形成在栅电极上的半导体层; 以及多个薄膜晶体管，每个薄膜晶体管具有形成在栅电极和半导体层上以彼此间隔开的源电极和漏电极。 多个薄膜晶体管中的至少一个是在源极和漏极之间不具有半导体层的虚设薄膜晶体管。

公开(公告)号：US08174478B2

公开(公告)日：2012-05-08

申请号：US11760174

申请日：2007-06-08

Applicant: Sung-Man Kim ,  Hong-Woo Lee ,  Byeong-Jae Ahn ,  Young-Geol Song ,  Bong-Jun Lee ,  Yeon-Kyu Moon ,  Kyung-Wook Kim ,  Jin-Suk Seo

Inventor： Sung-Man Kim ,  Hong-Woo Lee ,  Byeong-Jae Ahn ,  Young-Geol Song ,  Bong-Jun Lee ,  Yeon-Kyu Moon ,  Kyung-Wook Kim ,  Jin-Suk Seo

IPC: G09G3/36 ,  G11C19/00

CPC classification number: G11C19/184 ,  G09G3/3674 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2320/041

Abstract: A gate driving circuit and a display apparatus having the gate driving circuit include a pull-up part and a carry part pull up a present gate signal and a present carry signal, respectively, to a first clock during a first period within one frame. A pull-down part receives a next gate signal to discharge the present gate signal to a source power voltage. A pull-up driving part is connected to control terminals of the carry part and pull-up part (Q-node) to turn the carry part and pull-up part on and off. A floating preventing part prevents an output terminal of the carry part from being floated in response to the first clock during a second period within the one frame.

Abstract translation: 具有栅极驱动电路的栅极驱动电路和显示装置包括上拉部分和进位部分，分别在一帧内的第一时段期间将当前栅极信号和当前进位信号上拉到第一时钟。 下拉部分接收下一个栅极信号，以将当前栅极信号放电到源极电压。 上拉驱动部分连接到进位部分和上拉部分（Q-节点）的控制端子，以使进位部分和上拉部分打开和关闭。 浮动防止部件在一帧内的第二时段期间，响应于第一时钟防止进位部分的输出端子浮起。

公开(公告)号：US07955908B2

公开(公告)日：2011-06-07

申请号：US11674457

申请日：2007-02-13

Applicant: Hye-Young Ryu ,  Young-Hoon Yoo ,  Jang-Soo Kim ,  Sung-Man Kim ,  Kyung-Wook Kim ,  Hyang-Shik Kong ,  Young-Goo Song

Inventor： Hye-Young Ryu ,  Young-Hoon Yoo ,  Jang-Soo Kim ,  Sung-Man Kim ,  Kyung-Wook Kim ,  Hyang-Shik Kong ,  Young-Goo Song

IPC: H01L21/00

CPC classification number: G02F1/136227 ,  G02F2001/136236 ,  H01L27/1244 ,  H01L27/1248

Abstract: A thin film transistor array panel is provided, which includes: a gate line, a gate insulating layer, and a semiconductor layer sequentially formed on a substrate; a data line and a drain electrode formed at least on the semiconductor layer; a first passivation layer formed on the data line and the drain electrode and having a first contact hole exposing the drain electrode at least in part; a second passivation layer formed on the first passivation layer and having a second contact hole that is disposed on the first contact hole and has a first bottom edge placed outside the first contact hole and a second bottom edge placed inside the first contact hole; and a pixel electrode formed on the second passivation layer and connected to the drain electrode through the first and the second contact holes.

Abstract translation: 提供薄膜晶体管阵列面板，其包括：顺序地形成在基板上的栅极线，栅极绝缘层和半导体层; 至少形成在所述半导体层上的数据线和漏电极; 形成在所述数据线和所述漏电极上的第一钝化层，并且具有至少部分地暴露所述漏电极的第一接触孔; 第二钝化层，其形成在所述第一钝化层上，并且具有设置在所述第一接触孔上并具有放置在所述第一接触孔外部的第一底部边缘的第二接触孔和放置在所述第一接触孔内部的第二底部边缘; 以及形成在所述第二钝化层上并通过所述第一和第二接触孔连接到所述漏电极的像素电极。

公开(公告)号：US20100164854A1

公开(公告)日：2010-07-01

申请号：US12603764

申请日：2009-10-22

Applicant: Kyung-Wook Kim ,  Jong-Hoon Kim

Inventor： Kyung-Wook Kim ,  Jong-Hoon Kim

IPC: G09G3/36 ,  G11C19/00 ,  H01L21/82

CPC classification number: G09G3/3677 ,  G11C19/184 ,  H01L27/1288

Abstract: A gate drive circuit includes a shift register having stages connected to each other in series. An (m)-th stage (‘m’ is a natural number) includes an output part, a discharging part, a first holding part and a second holding part. The output part outputs the first clock signal as a gate signal in response to a first clock signal provided from an external device and discharges the gate signal in response to a second input signal. The output part includes a first transistor having a first channel length. The discharging part discharges a signal of the first node to the second voltage level. The first holding part maintains a signal of the first node at a level of the gate signal, and is discharged to the second voltage level. The first holding part includes a second transistor having a second channel length that is longer than the first channel length. The second holding part maintains a signal of the first node at a level of the second voltage level.

Abstract translation: 栅极驱动电路包括具有彼此串联连接的级的移位寄存器。 第（m）级（“m”是自然数）包括输出部分，排出部分，第一保持部分和第二保持部分。 输出部分响应于从外部设备提供的第一时钟信号而输出第一时钟信号作为门信号，并响应于第二输入信号而放电门信号。 输出部分包括具有第一通道长度的第一晶体管。 放电部分将第一节点的信号放电到第二电压电平。 第一保持部件将第一节点的信号保持在栅极信号的电平，并且被放电到第二电压电平。 第一保持部分包括具有比第一通道长度更长的第二通道长度的第二晶体管。 第二保持部将第一节点的信号维持在第二电压电平的电平。

公开(公告)号：US20100006725A1

公开(公告)日：2010-01-14

申请号：US12524436

申请日：2008-11-05

Applicant: Sang-Hoon Kim ,  Kyung-Wook Kim

Inventor： Sang-Hoon Kim ,  Kyung-Wook Kim

IPC: A47B96/06

CPC classification number: H04N5/64 ,  F16M11/10 ,  F16M11/2014 ,  F16M11/2085 ,  F16M11/2092 ,  F16M11/38 ,  F16M13/02 ,  Y10T403/32557 ,  Y10T403/32581 ,  Y10T403/32591

Abstract: Provided is a supporting apparatus for a display device. The supporting apparatus includes a stationary unit fixed at a fixing location, a device supporting unit supporting the display device, a connection unit connecting the stationary unit to the device supporting unit and guiding motion of the device supporting unit, and a tilting frictional unit interposed between the connection unit and the device supporting unit and guiding tilting motion of the device supporting unit in a vertical direction. The tilting frictional unit includes a first arc member fixed to the connection unit and a second arc member fixed to the device supporting unit. The first and second arc members contact each other to generate frictional force.

Abstract translation: 提供了一种用于显示装置的支撑装置。 支撑装置包括固定在固定位置的固定单元，支撑显示装置的装置支撑单元，将固定单元连接到装置支撑单元的连接单元和装置支撑单元的引导运动，以及夹在 连接单元和设备支撑单元，并且引导设备支撑单元在垂直方向上的倾斜运动。 倾斜摩擦单元包括固定到连接单元的第一弧形构件和固定到装置支撑单元的第二弧形构件。 第一和第二弧形构件彼此接触以产生摩擦力。

公开(公告)号：US20080012139A1

公开(公告)日：2008-01-17

申请号：US11770012

申请日：2007-06-28

Applicant: Hye-Young Ryu ,  Young-Hoon Yoo ,  Jang-Soo Kim ,  Sung-Man Kim ,  Kyung-Wook Kim ,  Hyang-Shik Kong ,  Young-Goo Song

Inventor： Hye-Young Ryu ,  Young-Hoon Yoo ,  Jang-Soo Kim ,  Sung-Man Kim ,  Kyung-Wook Kim ,  Hyang-Shik Kong ,  Young-Goo Song

IPC: H01L23/48

CPC classification number: G02F1/136227 ,  G02F2001/136236 ,  H01L27/1244 ,  H01L27/1248

Abstract: A thin film transistor array panel is provided, which includes: a gate line, a gate insulating layer, and a semiconductor layer sequentially formed on a substrate; a data line and a drain electrode formed at least on the semiconductor layer; a first passivation layer formed on the data line and the drain electrode and having a first contact hole exposing the drain electrode at least in part; a second passivation layer formed on the first passivation layer and having a second contact hole that is disposed on the first contact hole and has a first bottom edge, placed outside the first contact hole and a second bottom edge placed inside the first contact hole; and a pixel electrode formed on the second passivation layer and connected to the drain electrode through the first and the second contact holes.

Abstract translation: 提供薄膜晶体管阵列面板，其包括：顺序地形成在基板上的栅极线，栅极绝缘层和半导体层; 至少形成在所述半导体层上的数据线和漏电极; 形成在所述数据线和所述漏电极上的第一钝化层，并且具有至少部分地暴露所述漏电极的第一接触孔; 第二钝化层，其形成在所述第一钝化层上，并且具有设置在所述第一接触孔上并且具有放置在所述第一接触孔外部的第一底部边缘的第二接触孔和放置在所述第一接触孔内部的第二底部边缘; 以及形成在所述第二钝化层上并通过所述第一和第二接触孔连接到所述漏电极的像素电极。

公开(公告)号：US07223997B2

公开(公告)日：2007-05-29

申请号：US11008720

申请日：2004-12-08

Applicant: Kyung-Wook Kim ,  Beom-Jun Kim ,  Sung-Man Kim ,  Byeong-Jae Ahn ,  Young-Goo Song ,  Hyang-Shik Kong

Inventor： Kyung-Wook Kim ,  Beom-Jun Kim ,  Sung-Man Kim ,  Byeong-Jae Ahn ,  Young-Goo Song ,  Hyang-Shik Kong

IPC: H01L29/04

CPC classification number: H01L27/124 ,  G02F1/136209 ,  G02F1/136213 ,  G02F1/136227 ,  G02F2001/136218 ,  G02F2001/136222 ,  H01L27/1214 ,  H01L27/1288

Abstract: A thin film array panel is provided, which includes: a gate line formed on a substrate; a first insulating layer formed on the gate line; a semiconductor layer formed on the gate insulating layer; a data line formed on the gate insulating layer and intersecting the gate line; a drain electrode formed at least on the semiconductor layer; a conductor arranged in parallel to the data line; a second insulating layer formed on the data line, the drain electrode, and the conductor and having a first contact hole exposing a portion of the drain electrode; and a pixel electrode formed on the second insulating layer, connected to the drain electrode through the first contact hole, fully covering the data line.

Abstract translation: 提供薄膜阵列面板，其包括：形成在基板上的栅极线; 形成在栅极线上的第一绝缘层; 形成在所述栅极绝缘层上的半导体层; 形成在栅极绝缘层上并与栅极线相交的数据线; 至少形成在所述半导体层上的漏电极; 与数据线平行布置的导体; 形成在所述数据线上的第二绝缘层，所述漏电极和所述导体，并且具有暴露所述漏电极的一部分的第一接触孔; 以及形成在第二绝缘层上的像素电极，通过第一接触孔连接到漏电极，完全覆盖数据线。