公开(公告)号：US09343030B2

公开(公告)日：2016-05-17

申请号：US12840642

申请日：2010-07-21

申请人： Hyuk-Jin Kim ,  Kyung-ho Park ,  Sang Yong No ,  YoungJe Cho ,  Kook Hyun Choi ,  Yongjo Kim ,  Sung Hoon Kim ,  Hyo-Seop Kim

发明人： Hyuk-Jin Kim ,  Kyung-ho Park ,  Sang Yong No ,  YoungJe Cho ,  Kook Hyun Choi ,  Yongjo Kim ,  Sung Hoon Kim ,  Hyo-Seop Kim

IPC分类号： G09G5/02 ,  H03K3/00 ,  G09G3/36 ,  G11C19/28

CPC分类号： G09G3/3677 ,  G09G2300/0417 ,  G09G2310/0286 ,  G11C19/28

摘要： A gate driving circuit includes N stages (where N is a natural number greater than or equal to 2). The N stages are cascaded, and each of the N stages has a gate line connected thereto. A first stage group includes k stages of the N stages (where k is a natural number less than N), and the first stage group outputs a first output signal in response to a start signal. A second stage group (including N−k stages) generates a second output signal in response to the first output signal and outputs the second output signal to a corresponding gate line. The first stage group includes a first buffer and a second buffer, each of which receives the start signal. A size of the first buffer is smaller than a size of the second buffer.

摘要翻译： 门驱动电路包括N级（其中N是大于或等于2的自然数）。 N级级联，N级中的每一级具有与其连接的栅极线。 第一级组包括N级的k级（其中k是小于N的自然数），并且第一级组响应于起始信号输出第一输出信号。 第二级组（包括N-k级）响应于第一输出信号产生第二输出信号，并将第二输出信号输出到相应的栅极线。 第一级组包括第一缓冲器和第二缓冲器，每个缓冲器和第二缓冲器都接收起始信号。 第一缓冲器的尺寸小于第二缓冲器的尺寸。

公开(公告)号：US08912991B2

公开(公告)日：2014-12-16

申请号：US13188898

申请日：2011-07-22

申请人： Jong-In Kim ,  Min-Wook Park ,  Eun-Guk Lee ,  Young-Goo Song ,  Kyoung-Tai Han ,  Hyuk-Jin Kim ,  Hak-Bum Choi ,  Hyo-Seop Kim

发明人： Jong-In Kim ,  Min-Wook Park ,  Eun-Guk Lee ,  Young-Goo Song ,  Kyoung-Tai Han ,  Hyuk-Jin Kim ,  Hak-Bum Choi ,  Hyo-Seop Kim

IPC分类号： G09G3/04 ,  G09G3/36

CPC分类号： G09G3/3659 ,  G09G2300/0426 ,  G09G2300/0447 ,  G09G2300/0852 ,  G09G2300/0876

摘要： A liquid crystal display includes: a first gate line; a first data line crossing the first gate line; a first switching element connected with the first gate line and the first data line; a second switching element connected with the first gate line and the first data line; a first liquid crystal capacitor connected with the first switching element; a second liquid crystal capacitor connected with the second switching element; a boost switching element which is turned on during a time period not overlapping a time period during which the first switching element is turned on; and a boost capacitor including a first terminal connected with the boost switching element and a second terminal connected with the first liquid crystal capacitor.

摘要翻译： 液晶显示器包括：第一栅极线; 与第一栅极线交叉的第一数据线; 与第一栅极线和第一数据线连接的第一开关元件; 与第一栅极线和第一数据线连接的第二开关元件; 与第一开关元件连接的第一液晶电容器; 与第二开关元件连接的第二液晶电容器; 升压开关元件，其在与第一开关元件导通的时间段不重叠的时间段内导通; 以及升压电容器，包括与所述升压开关元件连接的第一端子和与所述第一液晶电容器连接的第二端子。

公开(公告)号：US08619218B2

公开(公告)日：2013-12-31

申请号：US13045400

申请日：2011-03-10

申请人： Hyuk-Jin Kim ,  Hyo-Taek Lim ,  Kweon-Sam Hong ,  Hyun Park ,  Tae-Hyeong Kim

发明人： Hyuk-Jin Kim ,  Hyo-Taek Lim ,  Kweon-Sam Hong ,  Hyun Park ,  Tae-Hyeong Kim

IPC分类号： G02F1/1335

CPC分类号： G02F1/133514 ,  G02F1/13394 ,  G02F2001/133388 ,  G02F2001/13396

摘要： A display substrate and a display device including the same are provided. The display substrate includes a first substrate which is divided into a display portion including pixel regions and a non-display portion including a region other than the display portion. Color filters are formed in the pixel regions of the substrate to respective thicknesses. At least one stepped pattern is formed on the non-display portion of the substrate and from the same material as used to form at least one of the color filters. The stepped patterns are formed at an area occupancy density of 20% or more of the non-display portion. A minimum distance is maintained between the stepped patterns and the pixel regions.

摘要翻译： 提供了显示基板和包括该显示基板的显示装置。 显示基板包括被分成包括像素区域的显示部分和包括除了显示部分之外的区域的非显示部分的第一基板。 在基板的像素区域中形成各个厚度的滤色器。 在基板的非显示部分上形成至少一个阶梯图案，并且与用于形成至少一个滤色器的相同材料形成。 阶梯图案形成在非显示部分的占有密度为20％以上的区域。 在阶梯图案和像素区域之间保持最小距离。

公开(公告)号：US20120236222A1

公开(公告)日：2012-09-20

申请号：US13188898

申请日：2011-07-22

申请人： Jong-In KIM ,  Min-Wook PARK ,  Eun-Guk LEE ,  Young-Goo SONG ,  Kyoung-Tai HAN ,  Hyuk-Jin KIM ,  Hak-Bum CHOI ,  Hyo-Seop KIM

发明人： Jong-In KIM ,  Min-Wook PARK ,  Eun-Guk LEE ,  Young-Goo SONG ,  Kyoung-Tai HAN ,  Hyuk-Jin KIM ,  Hak-Bum CHOI ,  Hyo-Seop KIM

IPC分类号： G02F1/136

CPC分类号： G09G3/3659 ,  G09G2300/0426 ,  G09G2300/0447 ,  G09G2300/0852 ,  G09G2300/0876

摘要： A liquid crystal display includes: a first gate line; a first data line crossing the first gate line; a first switching element connected with the first gate line and the first data line; a second switching element connected with the first gate line and the first data line; a first liquid crystal capacitor connected with the first switching element; a second liquid crystal capacitor connected with the second switching element; a boost switching element which is turned on during a time period not overlapping a time period during which the first switching element is turned on; and a boost capacitor including a first terminal connected with the boost switching element and a second terminal connected with the first liquid crystal capacitor.

摘要翻译： 液晶显示器包括：第一栅极线; 与第一栅极线交叉的第一数据线; 与第一栅极线和第一数据线连接的第一开关元件; 与第一栅极线和第一数据线连接的第二开关元件; 与第一开关元件连接的第一液晶电容器; 与第二开关元件连接的第二液晶电容器; 升压开关元件，其在与第一开关元件导通的时间段不重叠的时间段内导通; 以及升压电容器，包括与所述升压开关元件连接的第一端子和与所述第一液晶电容器连接的第二端子。

公开(公告)号：US08139176B2

公开(公告)日：2012-03-20

申请号：US12098176

申请日：2008-04-04

申请人： Kyung-Jin Lee ,  Kyung-Wook Kim ,  Hyuk-Jin Kim

发明人： Kyung-Jin Lee ,  Kyung-Wook Kim ,  Hyuk-Jin Kim

IPC分类号： G02F1/136

CPC分类号： G02F1/136209 ,  G02F2001/136236

摘要： A display substrate includes a gate line, a data line, a thin film transistor, a pixel electrode, and a light blocking layer. The data line is insulated from the gate line and crosses the gate line. The thin film transistor is connected to the gate line and the data line. The thin film transistor is formed in a pixel. The pixel electrode is formed in the pixel and connected to the thin film transistor. The light blocking layer is formed from a same layer as the data line, wherein the light blocking layer is adjacent to a side of the data line.

摘要翻译： 显示基板包括栅极线，数据线，薄膜晶体管，像素电极和遮光层。 数据线与栅极线绝缘，并与栅极线交叉。 薄膜晶体管连接到栅极线和数据线。 薄膜晶体管形成在像素中。 像素电极形成在像素中并连接到薄膜晶体管。 遮光层由与数据线相同的层形成，其中遮光层与数据线的一侧相邻。

公开(公告)号：US20110157263A1

公开(公告)日：2011-06-30

申请号：US12840642

申请日：2010-07-21

申请人： Hyuk-Jin KIM ,  Kyung-ho PARK ,  Sang Yong NO ,  YoungJe CHO ,  Kook Hyun CHOI ,  Yongjo KIM ,  Sung Hoon KIM ,  Hyo-Seop KIM

发明人： Hyuk-Jin KIM ,  Kyung-ho PARK ,  Sang Yong NO ,  YoungJe CHO ,  Kook Hyun CHOI ,  Yongjo KIM ,  Sung Hoon KIM ,  Hyo-Seop KIM

IPC分类号： G09G5/02 ,  H03K3/00

CPC分类号： G09G3/3677 ,  G09G2300/0417 ,  G09G2310/0286 ,  G11C19/28

摘要： A gate driving circuit includes N stages (where N is a natural number greater than or equal to 2). The N stages are cascaded, and each of the N stages has a gate line connected thereto. A first stage group includes k stages of the N stages (where k is a natural number less than N), and the first stage group outputs a first output signal in response to a start signal. A second stage group (including N−k stages) generates a second output signal in response to the first output signal and outputs the second output signal to a corresponding gate line. The first stage group includes a first buffer and a second buffer, each of which receives the start signal. A size of the first buffer is smaller than a size of the second buffer.

摘要翻译： 门驱动电路包括N级（其中N是大于或等于2的自然数）。 N级级联，N级中的每一级具有与其连接的栅极线。 第一级组包括N级的k级（其中k是小于N的自然数），并且第一级组响应于起始信号输出第一输出信号。 第二级组（包括N-k级）响应于第一输出信号产生第二输出信号，并将第二输出信号输出到相应的栅极线。 第一级组包括第一缓冲器和第二缓冲器，每个缓冲器和第二缓冲器都接收起始信号。 第一缓冲器的尺寸小于第二缓冲器的尺寸。

公开(公告)号：US07910931B2

公开(公告)日：2011-03-22

申请号：US11428980

申请日：2006-07-06

申请人： Hyuk-Jin Kim ,  Kyung-Wook Kim

发明人： Hyuk-Jin Kim ,  Kyung-Wook Kim

IPC分类号： H01L29/04

CPC分类号： H01L29/78669 ,  G02F1/136213 ,  G02F1/136227 ,  G02F1/1368 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/78678

摘要： A thin film transistor substrate including a thin film transistor having a drain electrode with an electrode portion, which overlaps with a semiconductor layer, and an extended portion, which extends from the electrode portion and has a portion overlapping with a storage electrode or storage electrode line. A passivation layer is arranged on the drain electrode, and it has a contact hole that partially exposes the extended portion of the drain electrode without exposing a step in the extended portion caused by the storage electrode or storage electrode line. A pixel electrode is arranged on the passivation layer and is electrically connected with the extended portion of the drain electrode through the contact hole.

摘要翻译： 一种薄膜晶体管基板，包括具有与半导体层重叠的具有电极部分的漏电极的薄膜晶体管和从电极部分延伸并具有与存储电极或存储电极线重叠的部分的延伸部分 。 钝化层布置在漏电极上，并且具有部分地暴露漏电极的延伸部分的接触孔，而不会暴露由存储电极或存储电极线引起的延伸部分中的台阶。 像素电极设置在钝化层上，并通过接触孔与漏电极的延伸部分电连接。

公开(公告)号：US07541225B2

公开(公告)日：2009-06-02

申请号：US11332076

申请日：2006-01-13

申请人： Bum-Ki Baek ,  Hyuk-Jin Kim

发明人： Bum-Ki Baek ,  Hyuk-Jin Kim

IPC分类号： H01L21/84

CPC分类号： H01L27/1288 ,  H01L27/1214

摘要： A method of manufacturing a thin film transistor array panel is provided, the method including forming a thin film transistor having a gate electrode, a source electrode, and a drain electrode on a substrate, forming a passivation layer on the source electrode and the drain electrode, forming a photoresist film on the passivation layer, selectively etching the passivation layer using the photoresist film as a mask, forming a conductive film, and removing the photoresist film along with the conductive film disposed on the photoresist film using a CMP (chemical mechanical polishing) process to form a pixel electrode being connected to the drain electrode.

摘要翻译： 提供一种制造薄膜晶体管阵列面板的方法，该方法包括在衬底上形成具有栅电极，源电极和漏电极的薄膜晶体管，在源电极和漏电极上形成钝化层 在钝化层上形成光致抗蚀剂膜，使用光致抗蚀剂膜作为掩模选择性地蚀刻钝化层，形成导电膜，以及使用CMP（化学机械抛光）与设置在光致抗蚀剂膜上的导电膜一起除去光致抗蚀剂膜 ）处理以形成连接到漏电极的像素电极。

公开(公告)号：US20080266477A1

公开(公告)日：2008-10-30

申请号：US11869197

申请日：2007-10-09

申请人： Bong-Jun LEE ,  Kyung-wook KIM ,  Jong-oh KIM ,  Sung-man KIM ,  Hong-woo LEE ,  Hyuk-jin KIM

发明人： Bong-Jun LEE ,  Kyung-wook KIM ,  Jong-oh KIM ,  Sung-man KIM ,  Hong-woo LEE ,  Hyuk-jin KIM

IPC分类号： H03K3/01 ,  G02F1/1368

CPC分类号： G09G3/3677 ,  G02F1/13454 ,  G09G2310/0286 ,  G09G2340/145 ,  G11C19/184

摘要： A gate driving circuit has a first stage which includes: a pull-up driving unit which receives a first carry signal from a second stage and outputs a control signal having first, second, third and fourth voltages to a first node during a preliminary period, a gate active period, a first gate inactive period and a second gate inactive period, respectively; a pull-up unit which receives the control signal and outputs a gate-on signal to a second node during the gate active period; a carry output unit which receives the control signal and outputs a second carry signal to a third stage during the gate active period; and a pull-down unit which receives a gate-off signal and the second carry signal from the second stage and outputs the control signal having the fourth voltage level to the first node during the second gate inactive period.

摘要翻译： 栅极驱动电路具有第一级，其包括：上拉驱动单元，其从初级阶段接收来自第二级的第一进位信号，并将具有第一，第二，第三和第四电压的控制信号输出到第一节点， 栅极有效期，第一栅极无效期和第二栅极非有效期; 上拉单元，其在所述门有效期间内接收所述控制信号并将栅极导通信号输出到第二节点; 进位输出单元，其在所述门有效期间内接收所述控制信号并将第二进位信号输出到第三级; 以及下拉单元，其从第二级接收栅极关闭信号和第二进位信号，并且在第二栅极非活动时段期间将具有第四电压电平的控制信号输出到第一节点。

公开(公告)号：US20060194376A1

公开(公告)日：2006-08-31

申请号：US11332076

申请日：2006-01-13

申请人： Bum-Ki Baek ,  Hyuk-Jin Kim

发明人： Bum-Ki Baek ,  Hyuk-Jin Kim

IPC分类号： H01L21/84 ,  H01L31/113

CPC分类号： H01L27/1288 ,  H01L27/1214

摘要： A method of manufacturing a thin film transistor array panel is provided, the method including forming a thin film transistor having a gate electrode, a source electrode, and a drain electrode on a substrate, forming a passivation layer on the source electrode and the drain electrode, forming a photoresist film on the passivation layer, selectively etching the passivation layer using the photoresist film as a mask, forming a conductive film, and removing the photoresist film along with the conductive film disposed on the photoresist film using a CMP (chemical mechanical polishing) process to form a pixel electrode being connected to the drain electrode.

摘要翻译： 提供一种制造薄膜晶体管阵列面板的方法，该方法包括在衬底上形成具有栅电极，源电极和漏电极的薄膜晶体管，在源电极和漏电极上形成钝化层 在钝化层上形成光致抗蚀剂膜，使用光致抗蚀剂膜作为掩模选择性地蚀刻钝化层，形成导电膜，以及使用CMP（化学机械抛光）与设置在光致抗蚀剂膜上的导电膜一起除去光致抗蚀剂膜 ）处理以形成连接到漏电极的像素电极。