公开(公告)号：US4398974A

公开(公告)日：1983-08-16

申请号：US366900

申请日：1982-04-09

Applicant: Kuen Chow ,  Jan Grinberg

Inventor： Kuen Chow ,  Jan Grinberg

IPC: C30B13/02 ,  H01L21/24 ,  H01L21/228

CPC classification number: C30B13/02 ,  H01L21/24

Abstract: A process is provided for fabricating a semiconductor device by thermal gradient zone melting, whereby metal-rich droplets such as aluminum migrate through a semiconductor wafer such as silicon to create conductive paths. One surface of the wafer in provided with a buffer layer thereon, which is placed directly on a heating surface. The buffer layer terminates the migration of the droplets to prevent alloying of the droplets with the heating surface.

Abstract translation: 提供了一种用于通过热梯度区熔化制造半导体器件的方法，由此富含金属的液滴（例如铝）迁移穿过诸如硅的半导体晶片以产生导电路径。 晶片的一个表面在其上设置有缓冲层，其直接放置在加热表面上。 缓冲层终止液滴的迁移，以防止液滴与加热表面的合金化。

公开(公告)号：US4523067A

公开(公告)日：1985-06-11

申请号：US366901

申请日：1982-04-09

Applicant: Roger H. Brown ,  Kuen Chow ,  Norman W. Goodwin ,  Jan Grinberg

Inventor： Roger H. Brown ,  Kuen Chow ,  Norman W. Goodwin ,  Jan Grinberg

IPC: C30B13/02 ,  H01L21/24 ,  H05B6/10

CPC classification number: H01L21/24 ,  C30B13/02

Abstract: An apparatus is provided for fabricating a semiconductor device by thermal gradient zone melting, whereby metal-rich droplets such as aluminum migrate through a semiconductor wafer such as silicon to create conductive paths. One surface of the wafer is placed directly on a heating surface to establish a high and uniform thermal gradient through the wafer. Heat in the wafer is removed from the other wafer surface. The apparatus for fabricating semiconductor devices utilizing temperature gradient zone melting comprises a base, heating means and heat sink means. Heating means comprises a platform having a generally planar heating surface adapted to receive the entire area of the one surface of at least one wafer. The heat sink means is spaced away from the other wafer surface to form a space therebetween, the space being adapted to receive a high heat conductive gas. The heat sink means and the gas cooperatively remove the heat in the wafer to enhance the establishment of the thermal gradient.

Abstract translation: 提供了一种用于通过热梯度区熔化来制造半导体器件的装置，由此诸如铝的富金属液滴迁移通过诸如硅的半导体晶片以产生导电路径。 将晶片的一个表面直接放置在加热表面上，以建立穿过晶片的高均匀的热梯度。 将晶片中的热量从另一晶片表面移除。 利用温度梯度区熔化制造半导体器件的装置包括基座，加热装置和散热装置。 加热装置包括具有适于接收至少一个晶片的一个表面的整个区域的大致平面加热表面的平台。 散热装置与另一个晶片表面间隔开以形成它们之间的空间，该空间适于接收高导热气体。 散热装置和气体协同地去除晶片中的热量以增强热梯度的建立。

公开(公告)号：US4275410A

公开(公告)日：1981-06-23

申请号：US964547

申请日：1978-11-29

Applicant: Jan Grinberg ,  Alexander D. Jacobson ,  Kuen Chow

Inventor： Jan Grinberg ,  Alexander D. Jacobson ,  Kuen Chow

IPC: H01L21/76 ,  G06F15/80 ,  H01L21/24 ,  H01L21/3205 ,  H01L21/822 ,  H01L23/48 ,  H01L23/538 ,  H01L25/065 ,  H01L27/00 ,  H01L27/04

CPC classification number: H01L24/72 ,  H01L21/24 ,  H01L23/5385 ,  H01L25/0657 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01049 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025

Abstract: A large scale parallel architecture in which many parallel channels numbering 10.sup.2 or more operate simultaneously to create a natural and efficient organization for processing two-dimensional arrays of data. The architecture comprises a plurality of stack integrated circuit wafers having top and bottom surfaces, electric signal paths extending through each of the wafers between the surfaces, and micro-interconnects (smaller than 50 mil) on the surfaces of adjacent wafers interconnecting the respective eletric signal paths with a topographical one-to-one correspondence.

Abstract translation: 大型并行架构，其中编号为102或更多的并行通道同时运行，以创建用于处理二维数据阵列的自然而有效的组织。 该架构包括具有顶表面和底表面的多个堆叠集成电路晶片，延伸穿过表面之间的每个晶片的电信号路径以及将相应电子信号互连的相邻晶片的表面上的微互连（小于50密耳） 具有地形一一对应的路径。

公开(公告)号：US4239347A

公开(公告)日：1980-12-16

申请号：US43077

申请日：1979-05-29

Applicant: Paul O. Braatz ,  Kuen Chow ,  Jan Grinberg

Inventor： Paul O. Braatz ,  Kuen Chow ,  Jan Grinberg

IPC: G02F1/1345 ,  G02F1/135

CPC classification number: G02F1/1345 ,  G02F1/1354

Abstract: A liquid crystal light valve having an improved counterelectrode structure. The light valve includes a layer of liquid crystal material which lies intermediate a photosensitive substrate of intrinsic semiconductive material and the counterelectrode. The upper surface of the substrate is characterized by a highly doped peripheral channel stop. The counterelectrode comprises electrically insulated inner and outer regions, the inner region substantially overlying only the intrinsic material interior said highly doped peripheral channel stop so that an electrical bias may be selectively applied, greatly enhancing the dark current breakdown voltage of the device.

Abstract translation: 一种具有改进的反电极结构的液晶光阀。 光阀包括位于本征半导体材料的光敏衬底和反电极之间的液晶材料层。 衬底的上表面的特征在于高度掺杂的外围通道停止。 反电极包括电绝缘的内部和外部区域，内部区域基本上仅覆盖内部材料内部，所述高度掺杂的外围通道停止，使得可以选择性地施加电偏压，大大增强了器件的暗电流击穿电压。

公开(公告)号：US4467340A

公开(公告)日：1984-08-21

申请号：US321360

申请日：1981-11-16

Applicant: Jonathan P. Rode ,  Kuen Chow

Inventor： Jonathan P. Rode ,  Kuen Chow

IPC: H01L27/148 ,  H01L29/78 ,  H01L27/14 ,  H01L29/56 ,  H01L31/00

CPC classification number: H01L27/14881

Abstract: Disclosed is a hybrid Schottky barrier focal plane, which includes a transparent semiconducting detector substrate of a first conductivity, with an array of detector groups disposed on the detector substrate, each group including a plurality of Schottky barrier detectors. An output contact is provided on the detector substrate for each of the detector groups. A field effect transistor for each detector includes a source region of a second conductivity type in the detector substrate and connected to the detector, a drain region of the second conductivity type in the detector substrate over the source and drain regions for controlling the connection between the source region and the drain region. An array of output contacts are disposed on a semiconducting multiplexer substrate, which also includes a charge coupled circuit for converting parallel signals from the input contacts to a serial output signal. An array of coupling elements is provided to connect each of the output contacts on the detector substrate to one of the input contacts on the multiplexer substrate.

Abstract translation: 公开了一种混合肖特基势垒焦平面，其包括具有第一导电性的透明半导体检测器基底，具有设置在检测器基底上的检测器阵列阵列，每组包括多个肖特基势垒检测器。 在检测器基板上为每个检测器组提供输出触点。 用于每个检测器的场效应晶体管包括在检测器基板中的第二导电类型的源极区域并连接到检测器，在源极和漏极区域上的检测器衬底中的第二导电类型的漏极区域，用于控制 源极区和漏极区。 输出触点阵列设置在半导体多路复用器衬底上，该衬底还包括用于将来自输入触点的并行信号转换为串行输出信号的电荷耦合电路。 提供耦合元件的阵列以将检测器基板上的每个输出触点连接到多路复用器基板上的输入触点之一。

公开(公告)号：US4045302A

公开(公告)日：1977-08-30

申请号：US703412

申请日：1976-07-08

Applicant: Stephen R. Gibbs ,  Kuen Chow

Inventor： Stephen R. Gibbs ,  Kuen Chow

IPC: C25D5/02 ,  C25D11/06 ,  H01L21/316 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L21/31687 ,  C25D11/06 ,  C25D5/02 ,  H01L21/76877 ,  H01L21/76888

Abstract: A method of making a multilevel conductor pattern for a semiconductor device. An aluminum layer on the substrate surface provides a situs for first level conductors. Successive soft and hard anodization steps are advantageously used to provide excellent intralevel isolation and interlevel electrical connection in desired areas. First level conductor sites are masked and the two anodized films are selectively removed in the desired nonconductive areas. The remaining first level aluminum is completely anodized. An insulating layer is then deposited and vias are formed therethrough to connect a subsequently deposited second level metallization layer with the conductor sites.

Abstract translation: 制造半导体器件的多层导体图案的方法。 衬底表面上的铝层为第一级导体提供了一个位置。 连续的软和硬阳极氧化步骤有利地用于在期望的区域中提供优异的层间隔离和层间电连接。 第一级导体部位被掩蔽，并且两个阳极氧化膜在期望的非导电区域中选择性地去除。 剩余的一级铝完全阳极氧化。 然后沉积绝缘层，并且通过其形成通孔以将随后沉积的第二层金属化层与导体部位连接。