公开(公告)号：US20070220742A1

公开(公告)日：2007-09-27

申请号：US11467568

申请日：2006-08-28

Applicant: Kuang-Lin Lo ,  Yung-Hui Wang

Inventor： Kuang-Lin Lo ,  Yung-Hui Wang

IPC: H01R43/00 ,  G08B13/14 ,  G06K7/00

CPC classification number: H01R13/465 ,  H05K1/0266 ,  H05K1/0269 ,  H05K3/027 ,  H05K3/4644 ,  H05K2201/09781 ,  H05K2201/09927 ,  H05K2201/09936 ,  Y10T29/49117

Abstract: A method for fabricating an identification code is provided. First, a metallic film is provided for fabricating a circuit on a substrate, and a circuit area and a non-circuit area are formed on the metallic film after a patterning process. Next, an identification code is formed on the non-circuit area for the basis of production management and quality control.

Abstract translation: 提供了一种制造识别码的方法。 首先，在基板上设置用于制造电路的金属膜，并且在图案化工艺之后在金属膜上形成电路区域和非电路区域。 接下来，在生产管理和质量控制的基础上，在非电路区域上形成识别码。

公开(公告)号：US20050282314A1

公开(公告)日：2005-12-22

申请号：US11150346

申请日：2005-06-13

Applicant: Kuang-Lin Lo ,  Jen-Kuang Fang

Inventor： Kuang-Lin Lo ,  Jen-Kuang Fang

IPC: H01L21/44 ,  H05K3/24 ,  H05K3/40 ,  H05K3/42

CPC classification number: H05K3/242 ,  H05K3/403 ,  H05K3/42 ,  H05K2201/0959 ,  H05K2201/09645 ,  H05K2203/1581 ,  H05K2203/175

Abstract: Printed circuit boards and methods for fabricating the same. A via in a printed circuit board electrically connects to trace lines of the PCB, such that only one plating line is required to electrically connect a plating bus and the plating through hole. Thus, in an electroplating step, current can flow to fingers in the trace lines to plate an anti-oxidation metal layer thereon. The via is separated into several sub-vias to electrically isolate the plating line from trace lines and fingers, each of which connects to the plating line or the trace lines. Finally, at least one plating line remains, thus avoiding negative impact on electrical performance of an electronic device that uses the printed circuit board.

Abstract translation: 印刷电路板及其制造方法。 印刷电路板中的通孔电连接到PCB的迹线，使得仅需要一条电镀线来电镀连接电镀母线和电镀通孔。 因此，在电镀步骤中，电流可以流到迹线中的指状物，以在其上镀上抗氧化金属层。 通孔被分成几个子通孔，以将电镀线与痕迹线和手指电隔离，每条线连接到电镀线或迹线。 最后，保留至少一个电镀线，从而避免对使用印刷电路板的电子设备的电气性能的负面影响。

公开(公告)号：US06777793B2

公开(公告)日：2004-08-17

申请号：US10289852

申请日：2002-11-07

Applicant: Meng-Tsang Lee ,  Kuang-Lin Lo

Inventor： Meng-Tsang Lee ,  Kuang-Lin Lo

IPC: H01L2302

CPC classification number: H05K9/0067

Abstract: The present invention relates to a packaging substrate with electrostatic discharge protection. The packaging substrate is deposited in a packaging mold, and the packaging mold comprises a plurality of injection pins for pushing the packaging substrate out of the packaging mold. A first copper-mesh layer and a second copper-mesh layer of the packaging substrate are electrically connected to each other via position pins. A bottom side of the packaging substrate comprises a plurality of recesses in positions corresponding to positions of the injection pins. The recesses pass the second copper-mesh layer to electrically connect the injection pins to the second copper-mesh layer, and static electric charges are conducted to the injection pins via the second copper-mesh layer and away from the packaging substrate. It prevents dies to be packaged from damage due to electrostatic discharge so as to raise the yield rate of semiconductor package products.

Abstract translation: 本发明涉及具有静电放电保护的封装基板。 包装基材沉积在包装模具中，并且包装模具包括用于将包装基材推出包装模具的多个注射销。 封装基板的第一铜网层和第二铜网层通过位置引脚彼此电连接。 包装衬底的底侧包括与注射销的位置对应的位置的多个凹部。 凹槽通过第二铜网层以将注射针电连接到第二铜网层，并且静电荷通过第二铜网层并且远离封装衬底被引导到注射销。 它可以防止模具由于静电放电而受到损坏，从而提高半导体封装产品的成品率。

公开(公告)号：US20070087480A1

公开(公告)日：2007-04-19

申请号：US11613195

申请日：2006-12-20

Applicant: Su TAO ,  Kuang-Lin Lo ,  Tsung-Sheng Lee ,  Yaw-Yuh Yang ,  Yuan-Kai Tao

Inventor： Su TAO ,  Kuang-Lin Lo ,  Tsung-Sheng Lee ,  Yaw-Yuh Yang ,  Yuan-Kai Tao

IPC: H01L21/78

CPC classification number: H01L24/97 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/4334 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/05599 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The present invention relates to a method for manufacturing a semiconductor chip package structure including the following steps. A substrate is provided. A plurality of chips are assembled onto the substrate and are electrically connected with the substrate. A stiffener is assembled onto the substrate and the stiffener has a top surface and a bottom surface facing the substrate. A molding compound is formed to cover the semiconductor chip, the substrate, the top surface and the bottom surface of the stiffener. Afterwards, a singulation step is performed to cut the molding compound, the substrate and the stiffener.

Abstract translation: 本发明涉及一种制造半导体芯片封装结构的方法，包括以下步骤。 提供基板。 将多个芯片组装到基板上并与基板电连接。 加强件组装在基底上，并且加强件具有面向基底的顶表面和底表面。 形成模塑料以覆盖加强件的半导体芯片，基板，顶表面和底表面。 然后，进行切割步骤以切割模塑料，基材和加强件。

公开(公告)号：US06942478B2

公开(公告)日：2005-09-13

申请号：US10268161

申请日：2002-10-10

Applicant: Meng-Tsang Lee ,  Kuang-Lin Lo

Inventor： Meng-Tsang Lee ,  Kuang-Lin Lo

IPC: B29C45/14 ,  B29C45/20 ,  B29C45/27 ,  B29C45/37 ,  H01L23/28

CPC classification number: B29C45/372 ,  B29C45/14655 ,  B29C45/2701

Abstract: The present invention relates to a packaging mold with electrostatic discharge protection comprising a pot block and at least one receiver. The pot block comprises a plurality of pots and runners. Each of the pots branches and connects the runners for injecting molding compound into the runners through the pots. The receiver for supporting a plurality of substrate plates connects the runners for receiving the molding compound from the runners to package the dice on the substrate plates. Each receiver comprises a receiving surface contacting the substrate plate; wherein the receiving surface is roughened to reduce static electric charges generated when separating the substrate plates and the packaging mold. Additionally, the surfaces of the runners are roughened to reduce static electric charges generated in the runners when separating the molding compound and the runners. It prevents the dice packaged from damage due to static electric charges to raise the yield rate of semiconductor package products thereby.

Abstract translation: 本发明涉及一种具有静电放电保护的包装模具，其包括一个罐块和至少一个接收器。 罐块包括多个盆和流道。 每个花盆分支并连接浇道，用于通过盆将浇注料浇注到浇道中。 用于支撑多个基板的接收器连接用于从浇道接收模制化合物的流道，以将模具封装在基板上。 每个接收器包括接触基板的接收表面; 其中所述接收表面被粗糙化以减少在分离所述基板和所述包装模具时产生的静电。 此外，当分离模制化合物和流道时，滑动件的表面被粗糙化以减少流道中产生的静电荷。 它防止由于静电导致包装的骰子损坏，从而提高半导体封装产品的成品率。

公开(公告)号：US6163076A

公开(公告)日：2000-12-19

申请号：US325382

申请日：1999-06-04

Applicant: Chun-Chi Lee ,  Kuang-Lin Lo ,  Kuang-Chwn Chou ,  Shih-Chih Chen

Inventor： Chun-Chi Lee ,  Kuang-Lin Lo ,  Kuang-Chwn Chou ,  Shih-Chih Chen

IPC: H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H01L25/065 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L25/0657 ,  H01L23/3157 ,  H01L23/49531 ,  H01L23/49551 ,  H01L23/49575 ,  H01L23/49805 ,  H01L2224/16 ,  H01L2225/06517 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2224/0401

Abstract: A stacked structure of a semiconductor package mainly comprises a first chip, a second chip, a substrate and a lead frame. The first chip and the second chip are attached on the surface of the substrate by a plurality of solder bumps by means of flipchip bonding. Then, the first chip, the second chip and the substrate form a stacked structure. A plurality of plugs of the substrate is provided along an edge of the substrate so as to attach to a plurality of receptacles of the lead frame to form a semiconductor device. The plugs are attached to the receptacles of the lead frame by silver paste to form a semiconductor device in such a way that the first chip and the second chip electrically connect to the lead frame. In addition, the lead frame is bent to form a plurality of fingers, which is placed in a space that is formed by a sidewall of the chip and a surface of the substrate while it is assembled. An encapsulant covers the stacked structure, then the fingers are exposed on the surface of the encapsulant, so that the first chip and the second chip can be operated by means of the fingers.

Abstract translation: 半导体封装的堆叠结构主要包括第一芯片，第二芯片，基板和引线框架。 第一芯片和第二芯片通过倒装芯片接合通过多个焊料凸块附接在基板的表面上。 然后，第一芯片，第二芯片和基板形成堆叠结构。 沿着基板的边缘设置多个基板插头，以便连接到引线框架的多个插座以形成半导体器件。 插头通过银膏附接到引线框架的插座以形成半导体器件，使得第一芯片和第二芯片电连接到引线框架。 此外，引线框架弯曲以形成多个指状物，其被放置在由芯片的侧壁和基板的表面组装在其中的表面形成的空间中。 密封剂覆盖堆叠结构，然后将指状物暴露在密封剂的表面上，使得第一芯片和第二芯片可以通过手指操作。

公开(公告)号：US20060091533A1

公开(公告)日：2006-05-04

申请号：US11258085

申请日：2005-10-26

Applicant: Yao-Ting Huang ,  Kuang-Lin Lo

Inventor： Yao-Ting Huang ,  Kuang-Lin Lo

IPC: H01L23/48 ,  H01L21/50

CPC classification number: H01L23/49838 ,  H01L21/4846 ,  H01L21/565 ,  H01L23/5386 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A multi-row substrate strip mainly comprises a plurality of first and second substrate units in parallel, a plurality of connecting bars, a degating metal layer and at least one plating layer. The connecting bars are used to connect the first substrate units and connect the second substrate units. The degating metal layer comprises a plurality of runner portions on the connecting bars, a plurality of first gate portions and a plurality of second gate portions. The first gate portions are formed on the first substrate units, and the second gate portions are formed on the second substrate units. The plating layer is formed on the first gate portions and the second gate portions, and exposes the runner portions, so as to save the plating material.

Abstract translation: 多列衬底条主要包括多个平行的第一和第二衬底单元，多个连接条，去金属层和至少一个镀层。 连接杆用于连接第一基板单元并连接第二基板单元。 脱金属层包括在连接杆上的多个流道部分，多个第一浇口部分和多个第二浇口部分。 第一栅极部分形成在第一基板单元上，并且第二栅极部分形成在第二基板单元上。 电镀层形成在第一栅极部分和第二栅极部分上，并露出流道部分，以便保存电镀材料。

公开(公告)号：US20050089594A1

公开(公告)日：2005-04-28

申请号：US10901039

申请日：2004-07-29

Applicant: Wei-Chih Wang ,  Kuang-Lin Lo ,  Yun-Lung Chang

Inventor： Wei-Chih Wang ,  Kuang-Lin Lo ,  Yun-Lung Chang

IPC: B29C45/14 ,  B29C45/76

CPC classification number: B29C45/7646 ,  B29C45/14639 ,  B29C2945/76056 ,  B29C2945/76063 ,  B29C2945/7626

Abstract: A molding apparatus mainly comprises a mold chase holder, a mold chase, a heater and a molding flowability sensor. The mold chase comprises a mold cavity and a via, wherein the via penetrates a mold-cavity surface of the mold cavity. The mold chase is accommodated by a mold chase holder and there is a heater, for heating the mold chase up, disposed therein. And the molding flowability sensor for measuring the molding flowability of the instant molding flow at the mold-cavity surface of the mold cavity is provided at the mold-cavity surface of the mold cavity.

Abstract translation: 成型装置主要包括模具支架，模具追踪器，加热器和成型流动性传感器。 模具追逐包括模腔和通孔，其中所述通孔穿过模腔的模腔表面。 模具追逐由模具夹持器容纳，并且设置有用于加热模具追加的加热器。 并且用于测量模腔的模腔表面处的即时成型流的成型流动性的成型流动性传感器设置在模腔的模腔表面。

公开(公告)号：US6093960A

公开(公告)日：2000-07-25

申请号：US330036

申请日：1999-06-11

Applicant: Su Tao ,  Kuang-Lin Lo ,  Hsin-Hsing Wei

Inventor： Su Tao ,  Kuang-Lin Lo ,  Hsin-Hsing Wei

IPC: H01L23/433 ,  H01L23/48 ,  H01L23/28 ,  H01L29/44

CPC classification number: H01L23/4334 ,  H01L2224/05599 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/85399 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/3025

Abstract: A semiconductor package has a die and a plurality of leads electrically connected to the die with bonding wires. A heat spreader has an upper face thermally contacted with the die. The heat spreader is formed by a copper core having at least a portion of surface sequentially coated with a metal medium layer and an insulation layer, wherein the metal medium layer has an adhesion degree with insulation material higher than copper. A package body encapsulates the die, the heat spreader and the plurality of leads, wherein the surface area of the heat spreader that contacts with the package body is coated with the metal medium layer and the insulation layer.

Abstract translation: 半导体封装具有管芯和多个引线，其使用接合线电连接到管芯。 散热器具有与模具热接触的上表面。 散热器由铜芯形成，铜芯具有依次涂覆有金属介质层和绝缘层的表面的至少一部分，其中金属介质层具有高于铜的绝缘材料的粘合度。 包装体封装模具，散热器和多个引线，其中与封装主体接触的散热器的表面积涂覆有金属介质层和绝缘层。

公开(公告)号：US07511366B2

公开(公告)日：2009-03-31

申请号：US11258085

申请日：2005-10-26

Applicant: Yao-Ting Huang ,  Kuang-Lin Lo

Inventor： Yao-Ting Huang ,  Kuang-Lin Lo

IPC: H01L23/02

CPC classification number: H01L23/49838 ,  H01L21/4846 ,  H01L21/565 ,  H01L23/5386 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A multi-row substrate strip mainly includes a plurality of first and second substrate units in parallel, a plurality of connecting bars, a degating metal layer and at least one plating layer. The connecting bars are used to connect the first substrate units and connect the second substrate units. The degating metal layer includes a plurality of runner portions on the connecting bars, a plurality of first gate portions and a plurality of second gate portions. The first gate portions are formed on the first substrate units, and the second gate portions are formed on the second substrate units. The plating layer is formed on the first gate portions and the second gate portions, and exposes the runner portions, so as to save the plating material.

Abstract translation: 多排衬底条主要包括多个平行的第一和第二衬底单元，多个连接条，去金属层和至少一个镀层。 连接杆用于连接第一基板单元并连接第二基板单元。 脱金属层包括连接杆上的多个流道部分，多个第一栅极部分和多个第二栅极部分。 第一栅极部分形成在第一基板单元上，并且第二栅极部分形成在第二基板单元上。 电镀层形成在第一栅极部分和第二栅极部分上，并露出流道部分，以便保存电镀材料。