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100 条记录 (耗时 0.036 秒)

    Power electronic devices, methods of manufacturing the same, and integrated circuit modules including the same
    1.
    发明授权
    Power electronic devices, methods of manufacturing the same, and integrated circuit modules including the same 有权
    电力电子装置及其制造方法以及包括其的集成电路模块

    公开(公告)号：US08513705B2

    公开(公告)日：2013-08-20

    申请号：US12923126

    申请日：2010-09-03

    申请人： Jong-seob Kim ,  Ki-ha Hong ,  Jae-joon Oh ,  Hyuk-soon Choi ,  In-jun Whang ,  Jai-kwang Shin

    发明人： Jong-seob Kim ,  Ki-ha Hong ,  Jae-joon Oh ,  Hyuk-soon Choi ,  In-jun Whang ,  Jai-kwang Shin

    IPC分类号： H01L29/778 ,  H01L21/335

    CPC分类号： H01L29/207 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787

    摘要： Power electronic devices including 2-dimensional electron gas (2DEG) channels and methods of manufacturing the same. A power electronic device includes lower and upper material layers for forming a 2DEG channel, and a gate contacting an upper surface of the upper material layer. A region below the gate of the 2DEG channel is an off region where the density of a 2DEG is reduced or zero. The entire upper material layer may be continuous and may have a uniform thickness. A region of the upper material layer under the gate contains an impurity for reducing or eliminating a lattice constant difference between the lower and upper material layers.

    摘要翻译： 包括二维电子气体（2DEG）通道的电力电子装置及其制造方法。 电力电子设备包括用于形成2DEG通道的下部和上部材料层，以及与上部材料层的上表面接触的栅极。 2DEG通道的栅极下方的区域是2DEG的密度减小或为零的截止区域。 整个上部材料层可以是连续的并且可以具有均匀的厚度。 在栅极下方的上部材料层的区域包含用于减少或消除下部和上部材料层之间的晶格常数差的杂质。

    Spin field effect logic devices
    2.
    发明授权
    Spin field effect logic devices 有权
    旋转场效应逻辑器件

    公开(公告)号：US08487358B2

    公开(公告)日：2013-07-16

    申请号：US12654349

    申请日：2009-12-17

    申请人： Ki-ha Hong ,  Jong-seob Kim ,  Jai-kwang Shin

    发明人： Ki-ha Hong ,  Jong-seob Kim ,  Jai-kwang Shin

    IPC分类号： H01L29/82 ,  H01L29/94

    CPC分类号： H01L29/66984 ,  B82Y25/00 ,  H01F1/401 ,  H01F10/1936 ,  H01F10/3254

    摘要： Provided are spin field effect logic devices, the logic devices including: a gate electrode; a channel formed of a magnetic material above the gate electrode to selectively transmit spin-polarized electrons; a source on the channel; and a drain and an output electrode on the channel outputting electrons transmitted from the source. The gate electrode may control a magnetization state of the channel in order to selectively transmit the electrons injected from the source to the channel.

    摘要翻译： 提供的是自旋场效应逻辑器件，逻辑器件包括：栅电极; 由栅电极上方的磁性材料形成的沟道，以选择性地透射自旋极化电子; 频道上的来源; 以及沟道上的漏极和输出电极，输出从源极发射的电子。 栅电极可以控制通道的磁化状态，以选择性地将从源引入的电子传输到通道。

    Chemical sensor using thin-film sensing member
    3.
    发明授权
    Chemical sensor using thin-film sensing member 有权
    化学传感器采用薄膜感应元件

    公开(公告)号：US08480959B2

    公开(公告)日：2013-07-09

    申请号：US13065000

    申请日：2011-05-02

    申请人： Ki-ha Hong ,  Hyuk-soon Choi ,  Jong-seob Kim ,  Jai-kwang Shin

    发明人： Ki-ha Hong ,  Hyuk-soon Choi ,  Jong-seob Kim ,  Jai-kwang Shin

    IPC分类号： G01N27/04 ,  G01N30/62

    CPC分类号： G01N29/036 ,  G01N2291/0257 ,  Y10S977/957

    摘要： Provided is a chemical sensor that may include a first electrode on a substrate, a sensing member covering the first electrode on the substrate, and a plurality of second electrodes on a surface of the sensing member exposing the surface of the sensing member. The chemical sensor may be configured to measure the change in electrical characteristics when a compound to be sensed is adsorbed on the sensing member. Provided also is a chemical sensor array including an array of chemical sensors.

    摘要翻译： 提供了一种化学传感器，其可以包括在基板上的第一电极，覆盖基板上的第一电极的感测构件和暴露感测构件的表面的感测构件的表面上的多个第二电极。 化学传感器可以被配置为当要感测的化合物吸附在感测构件上时测量电特性的变化。 还提供了包括化学传感器阵列的化学传感器阵列。

    POWER ELECTRONIC DEVICE AND METHOD OF MANUFACTURING THE SAME
    5.
    发明申请
    POWER ELECTRONIC DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    电力电子设备及其制造方法

    公开(公告)号：US20120037958A1

    公开(公告)日：2012-02-16

    申请号：US13208671

    申请日：2011-08-12

    申请人： In-jun Hwang ,  Jai-kwang Shin ,  Jae-joon Oh ,  Jong-seob Kim ,  Hyuk-soon Choi ,  Ki-ha Hong

    发明人： In-jun Hwang ,  Jai-kwang Shin ,  Jae-joon Oh ,  Jong-seob Kim ,  Hyuk-soon Choi ,  Ki-ha Hong

    IPC分类号： H01L29/778 ,  H01L21/335

    CPC分类号： H01L29/7787 ,  H01L29/2003 ,  H01L29/408 ,  H01L29/66462

    摘要： According to an example embodiment, a power electronic device includes a first semiconductor layer, a second semiconductor layer on a first surface of the first semiconductor layer, and a source, a drain, and a gate on the second semiconductor layer. The source, drain and gate are separate from one another. The power electronic device further includes a 2-dimensional electron gas (2DEG) region at an interface between the first semiconductor layer and the second semiconductor layer, a first insulating layer on the gate and a second insulating layer adjacent to the first insulating layer. The first insulating layer has a first dielectric constant and the second insulating layer has a second dielectric constant less than the first dielectric constant.

    摘要翻译： 根据示例性实施例，功率电子器件包括第一半导体层，第一半导体层的第一表面上的第二半导体层以及第二半导体层上的源极，漏极和栅极。 源极，漏极和栅极彼此分开。 电力电子设备还包括在第一半导体层和第二半导体层之间的界面处的二维电子气体（2DEG）区域，栅极上的第一绝缘层和与第一绝缘层相邻的第二绝缘层。 第一绝缘层具有第一介电常数，第二绝缘层具有小于第一介电常数的第二介电常数。

    Substrate structure, semiconductor device fabricated from the same, and method of fabricating the semiconductor device
    10.
    发明授权
    Substrate structure, semiconductor device fabricated from the same, and method of fabricating the semiconductor device 有权
    基板结构，由其制造的半导体器件以及半导体器件的制造方法

    公开(公告)号：US08921890B2

    公开(公告)日：2014-12-30

    申请号：US13551217

    申请日：2012-07-17

    申请人： Hyuk-soon Choi ,  Jong-seob Kim ,  Jai-kwang Shin ,  Chang-yong Um ,  Jae-joon Oh ,  Jong-bong Ha ,  In-jun Hwang ,  Ki-ha Hong

    发明人： Hyuk-soon Choi ,  Jong-seob Kim ,  Jai-kwang Shin ,  Chang-yong Um ,  Jae-joon Oh ,  Jong-bong Ha ,  In-jun Hwang ,  Ki-ha Hong

    IPC分类号： H01L31/102

    CPC分类号： H01L29/7813 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/41741 ,  H01L29/66734

    摘要： According to example embodiments, a substrate structure may include a GaN-based third material layer, a GaN-based second material layer, a GaN-based first material layer, and a buffer layer on a non-GaN-based substrate. The GaN-based first material layer may be doped with a first conductive type impurity. The GaN-based second material layer may be doped with a second conductive type impurity at a density that is less than a density of the first conductive type impurity in the first GaN-based material layer. The GaN-based third material layer may be doped with a first conductive type impurity at a density that is less than the density of the first conductive type impurity of the GaN-based first material layer. After a second substrate is attached onto the substrate structure, the non-GaN-based substrate may be removed and a GaN-based vertical type semiconductor device may be fabricated on the second substrate.

    摘要翻译： 根据示例实施例，衬底结构可以包括GaN基第三材料层，GaN基第二材料层，GaN基第一材料层和非GaN基衬底上的缓冲层。 GaN基第一材料层可以掺杂有第一导电类型的杂质。 GaN基第二材料层可以以小于第一GaN基材料层中的第一导电类型杂质的密度的密度掺杂第二导电型杂质。 GaN基第三材料层可以以比GaN基第一材料层的第一导电类型杂质的密度小的密度掺杂第一导电型杂质。 在将第二衬底附着到衬底结构上之后，可以去除非GaN基衬底，并且可以在第二衬底上制造GaN基垂直型半导体器件。