公开(公告)号：US20060286689A1

公开(公告)日：2006-12-21

申请号：US11453827

申请日：2006-06-16

申请人： Kazumi Watase ,  Akio Nakamura ,  Katsumi Ootani

发明人： Kazumi Watase ,  Akio Nakamura ,  Katsumi Ootani

IPC分类号： H01L21/00

CPC分类号： H01L22/14 ,  G01R31/2853 ,  H01L23/3114 ,  H01L23/5228 ,  H01L2924/0002 ,  H01L2924/014 ,  H01L2924/00

摘要： A metal wire for inspection and an electrode for inspection are formed on a region of a semiconductor substrate where a metal wire and an electrode for external connection are not formed. The metal wire for inspection and the electrode for inspection electrically detect an open failure, a short-circuit failure and a leakage failure of the metal wire and a connection failure between an element electrode and the metal wire. A semiconductor wafer is subjected to an electrical test, so that it is possible to detect the aforementioned failures with good accuracy during a manufacturing process.

公开(公告)号：US07595557B2

公开(公告)日：2009-09-29

申请号：US11453827

申请日：2006-06-16

申请人： Kazumi Watase ,  Akio Nakamura ,  Katsumi Ootani

发明人： Kazumi Watase ,  Akio Nakamura ,  Katsumi Ootani

IPC分类号： H01L29/40

CPC分类号： H01L22/14 ,  G01R31/2853 ,  H01L23/3114 ,  H01L23/5228 ,  H01L2924/0002 ,  H01L2924/014 ,  H01L2924/00

摘要： A metal wire for inspection and an electrode for inspection are formed on a region of a semiconductor substrate where a metal wire and an electrode for external connection are not formed. The metal wire for inspection and the electrode for inspection electrically detect an open failure, a short-circuit failure and a leakage failure of the metal wire and a connection failure between an element electrode and the metal wire. A semiconductor wafer is subjected to an electrical test, so that it is possible to detect the aforementioned failures with good accuracy during a manufacturing process.

摘要翻译： 在不形成金属线和外部连接用电极的半导体基板的区域上形成检查用金属线和检查用电极。 用于检查的金属线和用于检查的电极电检测金属线的开路故障，短路故障和漏电故障以及元件电极和金属线之间的连接故障。 对半导体晶片进行电气测试，从而可以在制造过程中以高精度检测上述故障。

公开(公告)号：US20070052106A1

公开(公告)日：2007-03-08

申请号：US10976914

申请日：2004-11-01

申请人： Kazumi Watase ,  Akio Nakamura ,  Minoru Fujisaku ,  Hiroki Naraoka ,  Takahiro Nakano

发明人： Kazumi Watase ,  Akio Nakamura ,  Minoru Fujisaku ,  Hiroki Naraoka ,  Takahiro Nakano

IPC分类号： H01L23/48 ,  H01L21/4763

CPC分类号： H01L23/3114 ,  H01L23/544 ,  H01L24/10 ,  H01L24/13 ,  H01L2223/5448 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05147 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01065 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2924/00014

摘要： A first mark formed simultaneously with the process step for forming a layer of metal interconnects is partly exposed at two parallel side surfaces of the separated semiconductor device or one side surface thereof to have a rectangular shape. This allows the identification of the orientation and product information of the semiconductor device in a small semiconductor device.

摘要翻译： 与用于形成金属互连层的工艺步骤同时形成的第一标记部分地暴露在分离的半导体器件的两个平行的侧表面或其一个侧表面上以具有矩形形状。 这允许在小型半导体器件中识别半导体器件的取向和产品信息。

公开(公告)号：US06559528B2

公开(公告)日：2003-05-06

申请号：US09785503

申请日：2001-02-20

申请人： Kazumi Watase ,  Hiroaki Fujimoto ,  Ryuichi Sahara ,  Nozomi Shimoishizaka ,  Takahiro Kumakawa ,  Kazuyuki Kaino ,  Yoshifumi Nakamura

发明人： Kazumi Watase ,  Hiroaki Fujimoto ,  Ryuichi Sahara ,  Nozomi Shimoishizaka ,  Takahiro Kumakawa ,  Kazuyuki Kaino ,  Yoshifumi Nakamura

IPC分类号： H01L23498

CPC分类号： H01L24/97 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/49872 ,  H01L24/45 ,  H01L24/48 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05599 ,  H01L2224/05647 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/85399 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2224/45015 ,  H01L2924/207

摘要： Disclosed is a semiconductor device 10 comprising a first semiconductor element 11 with an arrangement of first element electrodes 12, a second semiconductor element 13 with an arrangement of second element electrodes 14, a connection member 15 electrically connecting together a portion 12b of the first element electrodes 12 and the second element electrodes 14, an insulation layer 17 covering a major surface 11a of the first semiconductor element 11 and a backside surface 13b of the second semiconductor element 13, a wiring layer 22 formed on the insulation layer 17 and electrically connected to the first element electrode portion 12b exposed in an opening portion 21, and an external electrode 23 formed, as a portion of the wiring layer 22, on the insulation layer 17.

摘要翻译： 公开了一种半导体器件10，其包括具有第一元件电极12的布置的第一半导体元件11，具有第二元件电极14的布置的第二半导体元件13，将第一元件电极的部分12b电连接在一起的连接构件15 12和第二元件电极14，覆盖第一半导体元件11的主表面11a和第二半导体元件13的背面13b的绝缘层17，形成在绝缘层17上并电连接到第二半导体元件13的布线层22的布线层22。 露出在开口部分21中的第一元件电极部分12b和作为布线层22的一部分形成在绝缘层17上的外部电极23。

公开(公告)号：US4863830A

公开(公告)日：1989-09-05

申请号：US225665

申请日：1988-07-29

申请人： Eiichi Okutsu ,  Kazumi Watase

发明人： Eiichi Okutsu ,  Kazumi Watase

IPC分类号： G03C1/06 ,  G03C5/29 ,  G03C5/305

CPC分类号： G03C5/305

摘要： A process for hard tone development of a silver halide photographic light-sensitive material is described, comprising developing an imagewise exposed negative type silver halide photographic light-sensitive material in the presence of hydrazine, usig a developing solution comprising (1) a developing agent, (2) 0.25 mol/l or more of sulfite and (3) a compound represented by the general formula (I) and having a pH value of 10.5 to 12.3: ##STR1## wherein R.sub.1 and R.sub.2 represent each an alkyl group of R.sub.1 and R.sub.2 may form a ring by linking each other, R.sub.3 represents an alkyl group, an aryl group or a heterocyclic group, and R.sub.1, R.sub.2 and R.sub.3 may have substituents, A represents an alkylene group which may be substituted, and X represents --CONH--, --OCONH--, --NHCONH--, --NHCOO--, --COO--, --OCO--, --CO--, --NHCO--, --SO.sub.2 NH--, --NHSO.sub.2 --, --SO.sub.2 --or --O--.

摘要翻译： 描述了卤化银照相感光材料的硬色调发展方法，包括在肼的存在下显影成像曝光的负型卤化银照相感光材料，使用显影溶液，其包含（1）显影剂， （2）0.25mol / l以上的亚硫酸盐和（3）由通式（I）表示的化合物，其pH值为10.5〜12.3。（I）其中R1和R2各自表示烷基 R 1和R 2可以通过彼此连接形成环，R 3表示烷基，芳基或杂环基，R 1，R 2和R 3可以具有取代基，A表示可被取代的亚烷基，X表示 -CONH-， - OCONH-， - NHCONH-， - NHCOO - ， - COO - ， - OCO - ， - CO-， - NHCO - ， - SO 2 NH - ， - NHSO 2 - ， - SO 2 - 或-O-。

公开(公告)号：US4207157A

公开(公告)日：1980-06-10

申请号：US935391

申请日：1978-08-21

申请人： Hiroyuki Hirai ,  Sachio Matsushita ,  Isao Tsuyuki ,  Kazumi Watase

发明人： Hiroyuki Hirai ,  Sachio Matsushita ,  Isao Tsuyuki ,  Kazumi Watase

IPC分类号： G03C5/00 ,  G03C5/31 ,  G03D3/06 ,  C25B1/24 ,  B01D13/02 ,  C25B11/04

CPC分类号： G03D3/065 ,  G03C5/31

摘要： The concentration of halogen ions in a photographic developer is controlled at an almost constant value by determining the concentration of halogen ions in the developer by detecting the change in electric potential caused by the addition of silver ions to the solution, and controlling the electrical current supplied to a halogen ion removing means, such as an electrodialysis or an electrolysis unit having an anion exchange membrane, based on the result of the determination of halogen ions. By this method the amount of complementary developer added to a fatigued developer solution can be greatly reduced.

摘要翻译： 通过检测通过向溶液中加入银离子引起的电位变化来确定显影剂中的卤素离子的浓度，并且控制供给的电流，将照相显影剂中的卤素离子的浓度控制在几乎恒定的值 涉及一种卤素离子去除装置，例如具有阴离子交换膜的电渗析或电解装置，基于卤素离子的测定结果。 通过该方法，可以大大降低添加到疲劳显影剂溶液中的补充显影剂的量。

公开(公告)号：US07622792B2

公开(公告)日：2009-11-24

申请号：US11635656

申请日：2006-12-08

申请人： Kazumi Watase ,  Tsuyoshi Hamatani

发明人： Kazumi Watase ,  Tsuyoshi Hamatani

IPC分类号： H01L23/552 ,  H01L23/48

CPC分类号： H01L23/3192 ,  H01L23/585 ,  H01L23/60 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A conductive region electrically connected to a buffer coat film is formed on at least one corner of a semiconductor substrate, so that electricity charged on a package seal resin or a surface of the buffer coat film is allowed to flow toward the conductive region through a conductive path. Thus, density of the electricity charged on the package seal resin or the surface of the buffer coat film is lowered, and electric discharge can be suppressed. Since the electric discharge is suppressed, no high voltage is applied to an external input/output terminal. As a result, it is possible to prevent a circuit metal wire connected to an integrated circuit from being fused and an interlayer insulating film from being damaged.

摘要翻译： 在半导体衬底的至少一个角上形成与缓冲涂膜电连接的导电区域，使得充填在封装密封树脂或缓冲涂膜的表面上的电流通过导电的方式流向导电区域 路径。 因此，封装密封树脂或缓冲涂膜表面的电荷密度降低，能够抑制放电。 由于放电被抑制，所以不会对外部输入/输出端子施加高电压。 结果，可以防止连接到集成电路的电路金属线被熔化并且层间绝缘膜被损坏。

公开(公告)号：US20070132096A1

公开(公告)日：2007-06-14

申请号：US11635656

申请日：2006-12-08

申请人： Kazumi Watase ,  Tsuyoshi Hamatani

发明人： Kazumi Watase ,  Tsuyoshi Hamatani

IPC分类号： H01L23/48

CPC分类号： H01L23/3192 ,  H01L23/585 ,  H01L23/60 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A conductive region electrically connected to a buffer coat film is formed on at least one corner of a semiconductor substrate, so that electricity charged on a package seal resin or a surface of the buffer coat film is allowed to flow toward the conductive region through a conductive path. Thus, density of the electricity charged on the package seal resin or the surface of the buffer coat film is lowered, and electric discharge can be suppressed. Since the electric discharge is suppressed, no high voltage is applied to an external input/output terminal. As a result, it is possible to prevent a circuit metal wire connected to an integrated circuit from being fused and an interlayer insulating film from being damaged.

摘要翻译： 在半导体衬底的至少一个角上形成与缓冲涂膜电连接的导电区域，使得充填在封装密封树脂或缓冲涂膜的表面上的电流通过导电的方式流向导电区域 路径。 因此，封装密封树脂或缓冲涂膜表面的电荷密度降低，能够抑制放电。 由于放电被抑制，所以不会对外部输入/输出端子施加高电压。 结果，可以防止连接到集成电路的电路金属线被熔化并且层间绝缘膜被损坏。

公开(公告)号：US06914331B2

公开(公告)日：2005-07-05

申请号：US10442139

申请日：2003-05-21

申请人： Nozomi Shimoishizaka ,  Kazuyuki Kaino ,  Yoshifumi Nakamura ,  Keiji Miki ,  Kazumi Watase ,  Ryuichi Sahara

发明人： Nozomi Shimoishizaka ,  Kazuyuki Kaino ,  Yoshifumi Nakamura ,  Keiji Miki ,  Kazumi Watase ,  Ryuichi Sahara

IPC分类号： H01L21/768 ,  H01L21/822 ,  H01L23/12 ,  H01L23/31 ,  H01L23/48 ,  H01L23/522 ,  H01L27/04 ,  H01L23/498

CPC分类号： H01L23/3114 ,  H01L23/5227 ,  H01L2224/0401 ,  H01L2224/05555 ,  H01L2924/3011 ,  H01L2924/00014

摘要： A semiconductor device has a semiconductor chip, a first insulating film and an inductor. The semiconductor chip includes an integrated circuit formed on the main surface of the chip and a plurality of pad electrodes formed on the main surface of the chip and electrically connected to the integrated circuit. The first insulating film of an insulating resin material is formed on the main surface of the semiconductor chip, covers the integrated circuit, and includes a plurality of contact holes provided on the respective pad electrodes. The inductor is formed on the inductor formation region of the first insulating film, and both terminals of the inductor are connected to the pad electrodes through the contact holes, respectively. The inductor formation region of the first insulating film is formed thicker than a portion of the first insulating film around the contact hole.

摘要翻译： 半导体器件具有半导体芯片，第一绝缘膜和电感器。 半导体芯片包括形成在芯片的主表面上的集成电路和形成在芯片的主表面上并电连接到集成电路的多个焊盘电极。 绝缘树脂材料的第一绝缘膜形成在半导体芯片的主表面上，覆盖集成电路，并且包括设置在各个焊盘电极上的多个接触孔。 电感器形成在第一绝缘膜的电感器形成区域上，并且电感器的两个端子分别通过接触孔连接到焊盘电极。 第一绝缘膜的电感器形成区域形成为比接触孔周围的第一绝缘膜的一部分厚。

公开(公告)号：US07964475B2

公开(公告)日：2011-06-21

申请号：US11951441

申请日：2007-12-06

申请人： Yukiko Haraguchi ,  Takahiro Kumakawa ,  Takashi Yui ,  Kazumi Watase

发明人： Yukiko Haraguchi ,  Takahiro Kumakawa ,  Takashi Yui ,  Kazumi Watase

IPC分类号： H01L27/00 ,  H01L21/82

CPC分类号： H01L21/78

摘要： A modified layer 5 and an altered layer 8 are formed outside a dicing point of a dicing area 3. Thus without forming another interface between different physical properties on the dicing point, it is possible to prevent chipping from progressing along a crystal orientation from an interface between a semiconductor element 2 and a semiconductor substrate 1 and from a surface of the semiconductor element during dicing, thereby suppressing the development of chipping to the semiconductor element.

摘要翻译： 在切割区域3的切割点的外侧形成改质层5和改质层8.因此，在切割点的不同物理性质之间不形成另一界面，可以防止从界面 在半导体元件2和半导体基板1之间以及在切割期间从半导体元件的表面，从而抑制了对半导体元件的切屑的发展。