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    Back-sampling analog to digital converter
    4.
    发明授权
    Back-sampling analog to digital converter 失效
    反向采样模数转换器

    公开(公告)号：US5059982A

    公开(公告)日：1991-10-22

    申请号：US587089

    申请日：1990-09-24

    Applicant: Kantilal Bacrania ,  Chong I. Chi

    Inventor： Kantilal Bacrania ,  Chong I. Chi

    IPC: H03M1/08 ,  H03M1/46 ,  H03M1/80

    CPC classification number: H03M1/0836 ,  H03M1/466 ,  H03M1/804

    Abstract: Analog to digital conversion begins by terminating the acquisition phase of the analog input signal and immediately starting the successive approximation conversion phase upon receipt of a start conversion command. Upon the completion of the successive approximation conversion phase and latching the result, the array is rest if required. The comparator offset is sampled-and-held, if required, and the acquisition phase is initiated and continues until the receipt or occurrence of the next start conversion command.

    Abstract translation: 模拟数字转换通过终止模拟输入信号的采集阶段开始，并在接收到开始转换命令后立即开始逐次逼近转换阶段。 在逐次逼近转换阶段完成并锁存结果后，如果需要，阵列就会休息。 如果需要，比较器偏移被采样保持，并且采集阶段被启动并继续，直到接收或发生下一个启动转换命令。

    Fast level translator circuit
    5.
    发明授权
    Fast level translator circuit 失效
    快速电平转换电路

    公开(公告)号：US4897567A

    公开(公告)日：1990-01-30

    申请号：US257015

    申请日：1988-10-13

    Applicant: Kantilal Bacrania

    Inventor： Kantilal Bacrania

    IPC: H03K3/356

    CPC classification number: H03K3/356104

    Abstract: A level translator having a pair of cross-coupled pull-down field effect transistors, a pair of pull-up transistors, and a pair of additinal pull-down transistors wherein the additional pull-down transistors are operable to be on to initially pull down the respective node and the first pair of pull down transistors turn on to finish the pull down. The additional pull-down transistors became ineffective while the first pair of pull-down transistors are turned on hard.

    Abstract translation: 具有一对交叉耦合下拉场效应晶体管，一对上拉晶体管和一对附加下拉晶体管的电平转换器，其中附加下拉晶体管可操作以开始下拉 相应的节点和第一对下拉晶体管导通以完成下拉。 附加的下拉晶体管变得无效，而第一对下拉晶体管变硬。

    Track and hold with dual pump circuit
    6.
    发明授权
    Track and hold with dual pump circuit 失效
    跟踪和保持双泵电路

    公开(公告)号：US06731155B2

    公开(公告)日：2004-05-04

    申请号：US10308775

    申请日：2002-12-03

    Applicant: J. Mikko Hakkarainen ,  Kantilal Bacrania ,  Eric C. Sung ,  Hsin-Shu Chen ,  Bang-Sup Song ,  Mario Sanchez

    Inventor： J. Mikko Hakkarainen ,  Kantilal Bacrania ,  Eric C. Sung ,  Hsin-Shu Chen ,  Bang-Sup Song ,  Mario Sanchez

    IPC: H03K1716

    CPC classification number: H03M1/165 ,  H03M1/365

    Abstract: A dual pump circuit including a transmission gate and a dual charge pump. The transmission gate includes a p-channel transistor and an n-channel transistor, each having a control terminal and a pair of current terminals coupled between a dual pump input and a dual pump output. The dual charge pump includes first and second pump circuits, where each pump circuit is coupled to the dual pump input and to a control terminal of a corresponding one of the transmission gate transistors. Each pump circuit is operative to linearize operation of its corresponding transmission gate transistor by maintaining VGS—VT constant. The dual pump circuit is used in a track and hold circuit including at least one dual pump sampling circuit, at least one sampling capacitor, and a control circuit for controlling input signal sampling timing. Each dual pump sampling circuit includes the transmission gate and a dual charge pump.

    Abstract translation: 双泵电路，包括传输门和双电荷泵。 传输门包括一个p沟道晶体管和一个n沟道晶体管，每个具有一个控制端子和一对电流端子，耦合在一个双泵输入端和一个双泵输出端之间。 双电荷泵包括第一和第二泵电路，其中每个泵电路耦合到双泵输入和相应的一个传输栅晶体管的控制端。 每个泵电路通过维持VGS-VT恒定而使其对应的传输门晶体管的操作线性化。 双泵电路用于包括至少一个双泵采样电路，至少一个采样电容器和用于控制输入信号采样定时的控制电路的跟踪和保持电路。 每个双泵采样电路包括传输门和双电荷泵。

    Calibration of resistor ladder using difference measurement and parallel resistive correction
    7.
    发明授权
    Calibration of resistor ladder using difference measurement and parallel resistive correction 失效
    使用差分测量和并联电阻校正校准电阻梯

    公开(公告)号：US06628216B2

    公开(公告)日：2003-09-30

    申请号：US10207340

    申请日：2002-07-29

    Applicant: Hsin-Shu Chen ,  Kantilal Bacrania ,  Eric C. Sung ,  J. Mikko Hakkarainen ,  Bang-Sup Song ,  Brian L. Allen ,  Mario Sanchez

    Inventor： Hsin-Shu Chen ,  Kantilal Bacrania ,  Eric C. Sung ,  J. Mikko Hakkarainen ,  Bang-Sup Song ,  Brian L. Allen ,  Mario Sanchez

    IPC: H03M110

    CPC classification number: H03M1/165 ,  H03M1/365

    Abstract: A calibration system and method for a resistor ladder that employs relative measurement and adjustment between pairs of resistors. The system includes a resistor tree of complementary pairs of programmable resistors coupled to the resistor ladder, a measurement circuit that measures voltage differences between complementary pairs of programmable resistors, and control logic. The control logic controls the measurement circuit to measure a voltage difference between each complementary pair of programmable resistors and adjusts the relative resistance of each complementary pair of programmable resistors to equalize voltage. The measurement is facilitated by a sigma-delta ADC that converts a measured voltage difference into a bit stream. The programmable resistors are implemented with binary weighted resistors that are digitally adjusted one LSB at a time. Lower and upper adjustment thresholds may be employed to avoid unnecessary over-adjustments while maintaining a requisite level of accuracy.

    Abstract translation: 一种用于电阻梯的校准系统和方法，其采用电阻对之间的相对测量和调整。 该系统包括耦合到电阻梯的互补对可编程电阻器的电阻树，测量电路，其测量互补对可编程电阻器和控制逻辑之间的电压差。 控制逻辑控制测量电路来测量每对互补的可编程电阻之间的电压差，并调整每对互补可编程电阻对的相对电阻以均衡电压。 通过将测量的电压差转换为比特流的Σ-ΔADC便于测量。 可编程电阻通过二进制加权电阻实现，每次一个LSB​​数字调节。 可以采用较低和较高的调整阈值，以避免不必要的过度调整，同时保持必要的精度水平。

    Analog to digital converter using subranging and interpolation
    8.
    发明授权
    Analog to digital converter using subranging and interpolation 失效
    模数转换器采用子格局和插值

    公开(公告)号：US06570523B1

    公开(公告)日：2003-05-27

    申请号：US10097677

    申请日：2002-03-13

    Applicant: Kantilal Bacrania ,  Hsin-Shu Chen ,  Eric C. Sung ,  Bang-Sup Song ,  J. Mikko Hakkarainen ,  Brian L. Allen ,  Mario Sanchez

    Inventor： Kantilal Bacrania ,  Hsin-Shu Chen ,  Eric C. Sung ,  Bang-Sup Song ,  J. Mikko Hakkarainen ,  Brian L. Allen ,  Mario Sanchez

    IPC: H03M112

    CPC classification number: H03M1/165 ,  H03M1/365

    Abstract: A multistage ADC that subranges and interpolates, and that amplifies selected subranges to convert an analog signal to a stream of digital values. The ADC samples the analog signal and provides a stream of sample signals. A first stage flash converts each sample signal into a first multiple bit value and subranges a reference ladder according to the first multiple bit value into selected reference signals. Each additional secondary stage amplifies a selected subrange of signals from a prior stage, flash converts the amplified residual signals to provide an additional multiple bit value, interpolates each set of amplified residual signals and subranges the interpolated signals according to the corresponding multiple bit value. A final stage amplifies and flash converts to determine a final multiple bit value. An error corrector combines each set of multiple bit values into a digital value.

    Abstract translation: 一种多级ADC，用于对所选择的子范围进行放大和内插，以将模拟信号转换为数字值流。 ADC对模拟信号进行采样，并提供一个采样信号流。 第一级闪存将每个采样信号转换为第一多位值，并将根据第一多位值的参考梯形图子化为选定的参考信号。 每个附加的次级放大来自前一级的所选择的子信号，闪存转换放大的残留信号以提供附加的多位值，内插每组放大的残留信号，并根据相应的多位值对内插信号进行子范围调整。 最后一级放大并进行闪存转换，以确定最终的多位值。 误差校正器将每组多个位值组合成一个数字值。

    System and method of DC calibration of amplifiers
    10.
    发明授权
    System and method of DC calibration of amplifiers 失效
    放大器的直流校准系统和方法

    公开(公告)号：US06714886B2

    公开(公告)日：2004-03-30

    申请号：US10207470

    申请日：2002-07-29

    Applicant: Eric C. Sung ,  Kantilal Bacrania ,  Hsin-Shu Chen ,  J. Mikko Hakkarainen ,  Bang-Sup Song ,  Brian L. Allen ,  Mario Sanchez

    Inventor： Eric C. Sung ,  Kantilal Bacrania ,  Hsin-Shu Chen ,  J. Mikko Hakkarainen ,  Bang-Sup Song ,  Brian L. Allen ,  Mario Sanchez

    IPC: H03M112

    CPC classification number: H03M1/165 ,  H03M1/365

    Abstract: A compensation system for calibrating an amplifier having a compensation input including a sigma delta converter, a counter, a memory, adjust logic, a DAC, a pair of compensation capacitors, and a pair of current to voltage (I/V) converters. The converter converts an offset voltage to a bit stream. The counter stores a sum value indicative of the output offset. The memory stores a digital bias value. The adjust logic determines an adjust value based on the sum value and adjusts the stored digital bias value based on the adjust value. The DAC converts the digital bias value to a differential bias current. The compensation capacitors apply a compensation voltage to a compensation input of the amplifier. The I/V converters charge the compensation capacitors using the differential bias current. The adjust logic may use upper and lower thresholds and adjust the digital bias value by one LSB for each compensation cycle.

    Abstract translation: 一种用于校准具有包括Σ-Δ转换器，计数器，存储器，调整逻辑，DAC，一对补偿电容器和一对电流 - 电压（I / V）转换器的补偿输入的放大器的补偿系统。 转换器将偏移电压转换为位流。 计数器存储表示输出偏移量的和值。 存储器存储数字偏置值。 调整逻辑基于和值确定调整值，并根据调整值调整存储的数字偏置值。 DAC将数字偏置值转换为差分偏置电流。 补偿电容器将补偿电压施加到放大器的补偿输入。 I / V转换器使用差分偏置电流对补偿电容器充电。 调整逻辑可以使用上限和下限阈值，并且在每个补偿周期内将数字偏置值调整一个LSB​​。

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