公开(公告)号：US5481129A

公开(公告)日：1996-01-02

申请号：US391490

申请日：1995-02-21

Applicant: Glenn A. DeJong ,  Kantilal Bacrania ,  Michael D. Church ,  Gregory J. Fisher ,  John T. Gasner ,  Akira Ito ,  Jeffrey M. Johnston ,  Dave Kutchmarick ,  Choong-Sun Rhee

Inventor： Glenn A. DeJong ,  Kantilal Bacrania ,  Michael D. Church ,  Gregory J. Fisher ,  John T. Gasner ,  Akira Ito ,  Jeffrey M. Johnston ,  Dave Kutchmarick ,  Choong-Sun Rhee

IPC: G05F3/30 ,  G11C27/02 ,  H01L21/8249 ,  H01L27/02 ,  H01L27/06 ,  H03F1/52 ,  H03F3/50 ,  H03G1/00 ,  H03K5/15 ,  H03K17/22 ,  H03M1/16 ,  H03M1/36 ,  H01L29/8605

CPC classification number: H03K5/15 ,  G05F3/30 ,  G11C27/026 ,  H01L21/8249 ,  H01L27/0214 ,  H01L27/0623 ,  H01L27/0635 ,  H01L27/0688 ,  H03F1/523 ,  H03F3/505 ,  H03G1/0082 ,  H03K17/223 ,  H03M1/162 ,  H03F2200/294 ,  H03M1/365

Abstract: A two-step analog-to-digital converter and BiCMOS fabrication method. The fabrication method provides pseudosubstrate isolation of digital CMOS devices from the analog devices. The converter uses NPN current switching in a flash analog-to-digital converter and in a digital-to-analog converter for low noise operation. CMOS digital error correction and BiCMOS output drivers provide high packing density plus large output load handling. Timing control aggregates switching events and puts them into intervals when noise sensitive operations are inactive. The fabrication method uses a thin epitaxial layer with limited thermal processing to provide NPN and PNP devices with large breakdown and Early voltages. Laser trimmed resistors provide small long term drift due to dopant stabilization in underlying BPSG and low hydrogen nitride passivation.

Abstract translation: 两步模拟 - 数字转换器和BiCMOS制造方法。 该制造方法提供了数字CMOS器件与模拟器件的伪衬底隔离。 转换器在闪存模数转换器和数模转换器中使用NPN电流切换，以实现低噪声运行。 CMOS数字纠错和BiCMOS输出驱动器提供高封装密度和大输出负载处理。 定时控制聚合切换事件，并在噪声敏感操作无效时将其置于间隔。 该制造方法使用具有有限热处理的薄外延层来为NPN和PNP器件提供大的击穿和早期电压。 激光修整电阻器由于在底层BPSG和低氮化氢钝化中的掺杂剂稳定性而提供较小的长期漂移。

公开(公告)号：US06329260B1

公开(公告)日：2001-12-11

申请号：US09394802

申请日：1999-09-10

Applicant: Glenn Alan DeJong ,  Akira Ito ,  Choong-Sun Rhee ,  Jeffrey Johnston ,  Michael D. Church ,  Kantilal Bacrania

Inventor： Glenn Alan DeJong ,  Akira Ito ,  Choong-Sun Rhee ,  Jeffrey Johnston ,  Michael D. Church ,  Kantilal Bacrania

IPC: H01L21331

CPC classification number: G05F3/30 ,  G05F3/262 ,  G11C5/143 ,  G11C27/026 ,  H01L27/0214 ,  H01L27/0623 ,  H01L27/0688 ,  H03F1/523 ,  H03F3/505 ,  H03F2200/294 ,  H03G1/0082 ,  H03K5/15 ,  H03K17/223 ,  H03K2217/0018 ,  H03M1/162 ,  H03M1/365

Abstract: An integrated circuit has an isolation structure in the form of a double diode moat. The P substrate has P+ buried layers 8601 and 8602 on opposite sides of N+ buried layer 8605. Analog devices are formed behind one diode moat, digital CMOS devices are formed behind the other moat.

Abstract translation: 集成电路具有双二极管护城河形式的隔离结构。 P衬底在N +掩埋层8605的相对侧上具有P +掩埋层8601和8602.在一个二极管护套之后形成模拟器件，在另一个护城河之后形成数字CMOS器件。

公开(公告)号：US5994755A

公开(公告)日：1999-11-30

申请号：US739898

申请日：1996-10-30

Applicant: Glenn Alan DeJong ,  Akira Ito ,  Choong-Sun Rhee ,  Jeffrey Johnston ,  Michael D. Church ,  Kantilal Bacrania

Inventor： Glenn Alan DeJong ,  Akira Ito ,  Choong-Sun Rhee ,  Jeffrey Johnston ,  Michael D. Church ,  Kantilal Bacrania

IPC: G05F3/26 ,  G05F3/30 ,  G11C5/14 ,  G11C27/02 ,  H01L27/02 ,  H01L27/06 ,  H03F1/52 ,  H03F3/50 ,  H03G1/00 ,  H03K5/15 ,  H03K17/22 ,  H03M1/16 ,  H03M1/36

CPC classification number: G05F3/30 ,  G05F3/262 ,  G11C27/026 ,  G11C5/143 ,  H01L27/0214 ,  H01L27/0623 ,  H01L27/0688 ,  H03F1/523 ,  H03F3/505 ,  H03G1/0082 ,  H03K17/223 ,  H03K5/15 ,  H03M1/162 ,  H03F2200/294 ,  H03K2217/0018 ,  H03M1/365

Abstract: An integrated circuit has a pseudosubstrate 6060 with an isolation moat 9505. Substrate 6001 has one conductivity and a subcircuit region 6060 has an opposite conductivity. Digital CMOS devices are formed in the subcircuit over region 6060 and operate between zero to +5 volts. Analog devices are formed over the rest of the substrate and operate between plus and minus 5 volts. The moat 9505 isolates the digital CMOS devices from the analog devices.

Abstract translation: 集成电路具有带有隔离沟槽9505的伪衬底6060.衬底6001具有一个导电性，并且子电路区域6060具有相反的导电性。 数字CMOS器件形成在子电路区域6060上，并在零到+5伏特之间工作。 模拟器件形成在衬底的其余部分上，并在正负5伏之间工作。 护城河9505将数字CMOS设备与模拟设备隔离开来。