公开(公告)号：US5659261A

公开(公告)日：1997-08-19

申请号：US645139

申请日：1996-05-13

Applicant: Kantilal Bacrania ,  Chong In Chi ,  Gregory James Fisher

Inventor： Kantilal Bacrania ,  Chong In Chi ,  Gregory James Fisher

IPC: G05F3/26 ,  G05F3/30 ,  G11C27/02 ,  H01L27/02 ,  H01L27/06 ,  H03F1/52 ,  H03F3/50 ,  H03G1/00 ,  H03K5/15 ,  H03K17/22 ,  H03M1/16 ,  H03M1/36 ,  H03K17/60

CPC classification number: H03G1/0082 ,  G05F3/262 ,  G05F3/30 ,  G11C27/026 ,  H01L27/0214 ,  H01L27/0623 ,  H01L27/0688 ,  H03F1/523 ,  H03F3/505 ,  H03K17/223 ,  H03K5/15 ,  H03M1/162 ,  H03F2200/294 ,  H03M1/365

Abstract: The A-to-D converter 300 has an output buffer 320 with fourteen drivers each the same as driver 4100. Driver 4100 includes bipolar pull up pull down transistors 4102, 4103. Those transistors are both coupled to an output. Pull up transistor 4102 is coupled to a first reference voltage VDD; pull down transistor 4103 is coupled to a second or ground reference potential. A base drive circuit comprising a series connection between a resistor and a transistor 4121 to provide additional current to saturate the pull down transistor 4103 and thereby lower the collector-to-emitter voltage drop of transistor 4103 when transistor 4103 is turned on.

Abstract translation: A转D转换器300具有输出缓冲器320，其具有与驱动器4100相同的14个驱动器。驱动器4100包括双极上拉下拉晶体管4102,4103。这些晶体管都耦合到输出。 上拉晶体管4102耦合到第一参考电压VDD; 下拉晶体管4103耦合到第二或接地参考电位。 基极驱动电路包括电阻器和晶体管4121之间的串联连接，以提供额外的电流来使下拉晶体管4103饱和，从而当晶体管4103导通时降低晶体管4103的集电极 - 发射极电压降。

公开(公告)号：US5682111A

公开(公告)日：1997-10-28

申请号：US630874

申请日：1996-04-02

Applicant: Kantilal Bacrania ,  Chong In Chi ,  Gregory James Fisher

Inventor： Kantilal Bacrania ,  Chong In Chi ,  Gregory James Fisher

IPC: G05F3/26 ,  G05F3/30 ,  G11C27/02 ,  H01L27/02 ,  H01L27/06 ,  H03F1/52 ,  H03F3/50 ,  H03G1/00 ,  H03K5/15 ,  H03K17/22 ,  H03M1/16 ,  H03M1/36 ,  H03K3/01

CPC classification number: H03G1/0082 ,  G05F3/262 ,  G05F3/30 ,  G11C27/026 ,  H01L27/0214 ,  H01L27/0623 ,  H01L27/0688 ,  H03F1/523 ,  H03F3/505 ,  H03K17/223 ,  H03K5/15 ,  H03M1/162 ,  H03F2200/294 ,  H03M1/365

Abstract: Power monitoring circuit 5000 monitors a positive power supply Vcc and a negative power supply Vee. If either one or both power supplies fall below predetermined respective threshold values, a master reset pulse (MR) is generated. When both power supplies are at their normal operating level, the logic circuit 5040 generates a signal that enables operation of the circuit.

Abstract translation: 电力监控电路5000监视正电源Vcc和负电源Vee。 如果一个或两个电源低于预定的相应阈值，则产生主复位脉冲（MR）。 当两个电源都处于其正常工作电平时，逻辑电路5040产生一个能使电路工作的信号。