公开(公告)号：US12014881B2

公开(公告)日：2024-06-18

申请号：US17709338

申请日：2022-03-30

Applicant: KOREA ELECTRONICS TECHNOLOGY INSTITUTE

Inventor： Jong Min Yook ,  Je In Yu ,  Jun Chul Kim ,  Dong Su Kim

IPC: H01G4/33 ,  H01G4/005 ,  H01G4/012

CPC classification number: H01G4/33 ,  H01G4/005 ,  H01G4/012

Abstract: The present invention provides a method for manufacturing a high frequency capacitor, including preparing a substrate for formation of the capacitor, forming a dielectric layer at an upper surface of the substrate, forming an upper electrode at an upper surface of the dielectric layer, and removing a portion of a lower surface of the substrate, to expose a lower surface of the dielectric layer, and forming a lower electrode at the lower surface of the dielectric layer. The high frequency capacitor includes a dielectric layer having a uniform surface, a thick upper electrode, and a thick lower electrode and, as such, exhibits high quality factor (Q) even at a high frequency.

公开(公告)号：US11538770B2

公开(公告)日：2022-12-27

申请号：US16878727

申请日：2020-05-20

Applicant: Korea Electronics Technology Institute

Inventor： Jong Min Yook ,  Jun Chul Kim ,  Dong Su Kim

IPC: H01L23/64 ,  H01L49/02 ,  H01L23/00

Abstract: A semiconductor package includes a semiconductor chip including an electrode pad formed on the top surface thereof, a passive device embedded in the semiconductor package, the passive device having no functional electrode on the top surface thereof, a cover layer covering the semiconductor chip and the passive device, and at least one electrode pattern formed on the cover layer to transmit electrical signals. The cover layer includes at least one first opening formed to expose a region in which the functional electrode is to be formed. The electrode pattern includes a functional electrode portion formed in a region in which the functional electrode of the passive device is to be formed through the first opening. In the process of forming the electrode pattern, a functional electrode of the passive device is formed together therewith, thereby eliminating a separate step of manufacturing a functional electrode and thus reducing manufacturing costs.

公开(公告)号：US20180182842A1

公开(公告)日：2018-06-28

申请号：US15822772

申请日：2017-11-27

Applicant: KOREA ELECTRONICS TECHNOLOGY INSTITUTE

Inventor： Jun Chul Kim ,  Dong Su Kim ,  Jong Min Yook

IPC: H01L49/02 ,  H01G4/06

CPC classification number: H01L28/60 ,  H01G4/06

Abstract: In one embodiment of the present invention, there is provided an MIS capacitor, including: a lower electrode formed with a semiconductor substrate having electrical conductivity and through which an electrical signal passes at a lower surface thereof; an insulating layer formed on the lower electrode; an upper electrode formed on the insulating layer and through which the electrical signal passes at an upper surface thereof; and a first conductive layer formed on side surfaces of the lower electrode so that the electrical signal passing the lower surface and an upper surface of the lower electrode passes along the side surfaces of the lower electrode, wherein the first conductive layer has electro conductivity higher than the electro conductivity of the lower electrode.

公开(公告)号：US10170538B2

公开(公告)日：2019-01-01

申请号：US15822772

申请日：2017-11-27

Applicant: KOREA ELECTRONICS TECHNOLOGY INSTITUTE

Inventor： Jun Chul Kim ,  Dong Su Kim ,  Jong Min Yook

IPC: H01L29/94 ,  H01L49/02 ,  H01G4/06

Abstract: In one embodiment of the present invention, there is provided an MIS capacitor, including: a lower electrode formed with a semiconductor substrate having electrical conductivity and through which an electrical signal passes at a lower surface thereof; an insulating layer formed on the lower electrode; an upper electrode formed on the insulating layer and through which the electrical signal passes at an upper surface thereof; and a first conductive layer formed on side surfaces of the lower electrode so that the electrical signal passing the lower surface and an upper surface of the lower electrode passes along the side surfaces of the lower electrode, wherein the first conductive layer has electro conductivity higher than the electro conductivity of the lower electrode.

公开(公告)号：US09899315B2

公开(公告)日：2018-02-20

申请号：US14781991

申请日：2014-04-24

Applicant: KOREA ELECTRONICS TECHNOLOGY INSTITUTE

Inventor： Jun Chul Kim ,  Dong Su Kim ,  Se Hoon Park ,  Jong Min Yook

IPC: H01L23/522 ,  H01L23/48 ,  H01L49/02 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5222 ,  H01L23/5225 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/528 ,  H01L23/5329 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a wiring for a semiconductor device according to an aspect of the present invention includes: forming a predetermined pattern on a first surface of a silicon substrate by selectively etching the first surface; coating, with a metal layer, a selected area of the first surface, including an area whereat the predetermined pattern is formed; forming organic material in the first surface to fill an etched portion and cover the coated metal layer; forming a plurality of via holes in the organic material and connecting the metal wiring to the coated metal layer through the via holes; and grinding a second surface corresponding to the first surface to remove a part of the metal layer formed in the etched portion.

公开(公告)号：US11658374B2

公开(公告)日：2023-05-23

申请号：US15930404

申请日：2020-05-12

Applicant: KOREA ELECTRONICS TECHNOLOGY INSTITUTE

Inventor： Jong Min Yook ,  Jun Chul Kim ,  Dong Su Kim

IPC: H04B17/00 ,  H01P3/06 ,  H01P11/00 ,  H01L23/66

CPC classification number: H01P3/06 ,  H01L23/66 ,  H01P11/005 ,  H01L2223/6627

Abstract: A quasi-coaxial transmission line, a semiconductor package including the same and a method of manufacturing the same are disclosed. The quasi-coaxial transmission line includes a core, which is formed through an upper surface and a lower surface of a base substrate so as to transmit an electrical signal, and a shield, which is spaced apart from the core and which coaxially surrounds a side surface of the core, at least a portion of the shield being removed so as to form an open portion. The quasi-coaxial transmission line is capable of preventing distortion of an electrical signal at a portion thereof that is connected to an external circuit board and to reduce an area of a semiconductor package including the quasi-coaxial transmission line.

公开(公告)号：US11197372B2

公开(公告)日：2021-12-07

申请号：US16661244

申请日：2019-10-23

Applicant: KOREA ELECTRONICS TECHNOLOGY INSTITUTE

Inventor： Jong Min Yook ,  Jun Chul Kim ,  Dong Su Kim

IPC: H05K1/16 ,  H01G4/35 ,  H01G4/38

Abstract: An embodiment of the present invention provides a capacitor having a through hole structure and a manufacturing method therefor. The capacitor having the through hole structure includes: a baseboard having a through hole penetrating from an upper surface of the baseboard to a lower surface thereof; a first conductive layer formed on an internal surface of the through hole, and the upper surface of the baseboard, the lower surface thereof, or both the upper and lower surfaces thereof; a first dielectric layer formed on the first conductive layer; and a second conductive layer formed on the first dielectric layer.

公开(公告)号：US09984950B2

公开(公告)日：2018-05-29

申请号：US15441188

申请日：2017-02-23

Applicant: KOREA ELECTRONICS TECHNOLOGY INSTITUTE

Inventor： Jun Chul Kim ,  Dong Su Kim ,  Jong Min Yook

IPC: H01L23/52 ,  H01L23/367 ,  H01L23/14 ,  H01L23/13 ,  H01L23/373 ,  H01L23/485 ,  H01L21/52 ,  H01L21/56

CPC classification number: H01L23/3675 ,  H01L21/52 ,  H01L21/56 ,  H01L21/568 ,  H01L23/13 ,  H01L23/142 ,  H01L23/367 ,  H01L23/3735 ,  H01L23/3736 ,  H01L23/485 ,  H01L23/5389 ,  H01L2224/04105 ,  H01L2224/19

Abstract: Disclosed is a semiconductor package including: a base substrate provided with at least one cavity and made of a metallic material; at least one semiconductor chip mounted in the cavity; and a heat dissipating member arranged in a gap between an inner surface of the cavity and the semiconductor chip.