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    Write data mask method and system
    1.
    发明授权
    Write data mask method and system 有权
    写数据掩码的方法和系统

    公开(公告)号：US08429356B2

    公开(公告)日：2013-04-23

    申请号：US11359809

    申请日：2006-02-22

    申请人： Joseph D. Macri ,  Stephen Morein ,  Ming-Ju E. Lee ,  Lin Chen

    发明人： Joseph D. Macri ,  Stephen Morein ,  Ming-Ju E. Lee ,  Lin Chen

    IPC分类号： G06F13/00

    CPC分类号： G06F12/00 ,  G06F13/4234 ,  G06F13/4243 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/1096

    摘要： A method and system for performing byte-writes are described, where byte-writes involve writing only particular bytes of a multiple byte write operation. Embodiments include mask data that indicates which bytes are to be written in a byte-write operation. No dedicated mask pin(s) or dedicated mask line(s) are used. In one embodiment, the mask data is transmitted on data lines and store in response to a write_mask command. In one embodiment, the mask data is transmitted as part of the write command.

    摘要翻译： 描述了用于执行字节写入的方法和系统，其中字节写入仅涉及仅写入多字节写入操作的特定字节。 实施例包括指示在字节写入操作中要写入哪些字节的掩码数据。 不使用专用的掩码引脚或专用掩码线。 在一个实施例中，掩码数据在数据线上传输，并响应于write_mask命令存储。 在一个实施例中，掩模数据作为写入命令的一部分被发送。

    Dynamic bus inversion method and system
    2.
    发明授权
    Dynamic bus inversion method and system 有权
    动态总线反演方法及系统

    公开(公告)号：US07869525B2

    公开(公告)日：2011-01-11

    申请号：US11357291

    申请日：2006-02-17

    申请人： Joseph D. Macri ,  Stephen Morein ,  Ming-Ju E. Lee ,  Lin Chen

    发明人： Joseph D. Macri ,  Stephen Morein ,  Ming-Ju E. Lee ,  Lin Chen

    IPC分类号： H04B3/00

    CPC分类号： H04L25/4915 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/0814 ,  H04L7/0004 ,  H04L7/0008 ,  H04L7/0037 ,  H04L7/0337

    摘要： A dynamic bus inversion (DBI) method and system are described. In various embodiments, a transmitter transmits data over a multi-bit high-speed bus to a receiver. In an embodiment, the transmitter determines whether to invert the bus based on the number of data bits that will be transitioning to a new value. If it is determined that the bus is to be inverted, the transmitter encodes a DBI signal on a shared line of the bus. In an embodiment, the shared line is used for different purposes at different times, obviating the need for a dedicated line or pin for the encoded DBI signal. The receiver receives and decodes the DBI signal and, in response, appropriately decodes the received data.

    摘要翻译： 描述了动态总线反演（DBI）方法和系统。 在各种实施例中，发射机通过多比特高速总线向接收机发送数据。 在一个实施例中，发射机基于将要转换到新值的数据比特数来确定是否反转总线。 如果确定总线被反相，则发送器对总线的共享线路上的DBI信号进行编码。 在一个实施例中，共享线路在不同时间用于不同的目的，从而避免了对编码的DBI信号的专用线路或引脚的需要。 接收器接收并解码DBI信号，作为响应，对接收到的数据进行适当的解码。

    Error detection in high-speed asymmetric interfaces
    3.
    发明授权
    Error detection in high-speed asymmetric interfaces 有权
    高速非对称接口中的错误检测

    公开(公告)号：US08661300B1

    公开(公告)日：2014-02-25

    申请号：US13169977

    申请日：2011-06-27

    申请人： Joseph Macri ,  Stephen Morein ,  Claude Gauthier ,  Ming-Ju E. Lee ,  Lin Chen

    发明人： Joseph Macri ,  Stephen Morein ,  Claude Gauthier ,  Ming-Ju E. Lee ,  Lin Chen

    IPC分类号： G06F11/00

    CPC分类号： G06F11/10

    摘要： A system and method for detecting errors in high-speed asymmetric interfaces are described. Embodiments include transmitting digital data between a first system component and a second system component over a bidirectional interface, wherein the first component is significantly more intelligent than the second component. The first component controls many operations of the second component, including receiving a signature from the second component over an existing line of the interface. The signature received is compared to a signature stored by the first component. Both signatures correspond to a transaction over the interface. Based on the comparison, the first component determines whether the transaction was successful, and directs the second component as necessary.

    摘要翻译： 描述了用于检测高速非对称接口中的错误的系统和方法。 实施例包括通过双向接口在第一系统组件和第二系统组件之间传输数字数据，其中第一组件比第二组件明显更智能。 第一个组件控制第二个组件的许多操作，包括通过接口的现有行接收来自第二个组件的签名。 所接收的签名与由第一组件存储的签名进行比较。 两个签名对应于接口上的事务。 基于比较，第一个组件确定事务是否成功，并根据需要引导第二个组件。

    Asymmetrical IO Method and System
    4.
    发明申请
    Asymmetrical IO Method and System 有权
    非对称IO方法和系统

    公开(公告)号：US20090125747A1

    公开(公告)日：2009-05-14

    申请号：US12356804

    申请日：2009-01-21

    申请人： Stephen Morein ,  Joseph Macri ,  Claude Gauthier ,  Ming-Ju E. Lee ,  Lin Chen

    发明人： Stephen Morein ,  Joseph Macri ,  Claude Gauthier ,  Ming-Ju E. Lee ,  Lin Chen

    IPC分类号： G06F1/12

    CPC分类号： H04L7/02 ,  H04L7/0025 ,  H04L7/0091

    摘要： An asymmetrical IO method and system are described. In one embodiment, a host device includes shared resources for data synchronization of the host device and a client device. The shared resources include a shared phase interpolator. In an embodiment, data lines between the host and client are also used to transmit phase information from the client device to the host device, obviating the need for additional, dedicated lines or pins.

    摘要翻译： 描述了非对称IO方法和系统。 在一个实施例中，主机设备包括用于主机设备和客户端设备的数据同步的共享资源。 共享资源包括一个共享相位内插器。 在一个实施例中，主机和客户机之间的数据线也用于将相位信息从客户端设备发送到主机设备，从而避免了对额外的专用线或引脚的需要。

    Asymmetrical IO method and system
    5.
    发明授权
    Asymmetrical IO method and system 有权
    非对称IO方法和系统

    公开(公告)号：US07487378B2

    公开(公告)日：2009-02-03

    申请号：US11231078

    申请日：2005-09-19

    申请人： Stephen Morein ,  Joseph Macri ,  Claude Gauthier ,  Ming-Ju E. Lee ,  Lin Chen

    发明人： Stephen Morein ,  Joseph Macri ,  Claude Gauthier ,  Ming-Ju E. Lee ,  Lin Chen

    IPC分类号： G06F1/04 ,  G06F1/24 ,  G06F11/00

    CPC分类号： H04L7/02 ,  H04L7/0025 ,  H04L7/0091

    摘要： An asymmetrical IO method and system are described. In one embodiment, a host device includes shared resources for data synchronization of the host device and a client device. The shared resources include a shared phase interpolator. In an embodiment, data lines between the host and client are also used to transmit phase information from the client device to the host device, obviating the need for additional, dedicated lines or pins.

    摘要翻译： 描述了非对称IO方法和系统。 在一个实施例中，主机设备包括用于主机设备和客户端设备的数据同步的共享资源。 共享资源包括一个共享相位内插器。 在一个实施例中，主机和客户机之间的数据线也用于将相位信息从客户端设备发送到主机设备，从而避免了对额外的专用线或引脚的需要。

    Error detection in high-speed asymmetric interfaces utilizing dedicated interface lines
    6.
    发明授权
    Error detection in high-speed asymmetric interfaces utilizing dedicated interface lines 有权
    使用专用接口线路的高速非对称接口中的错误检测

    公开(公告)号：US08892963B2

    公开(公告)日：2014-11-18

    申请号：US11595619

    申请日：2006-11-09

    申请人： Joseph Macri ,  Stephen Morein ,  Claude Gauthier ,  Ming-Ju E. Lee ,  Lin Chen

    发明人： Joseph Macri ,  Stephen Morein ,  Claude Gauthier ,  Ming-Ju E. Lee ,  Lin Chen

    IPC分类号： G06F11/00 ,  H04L1/00 ,  G06F11/10 ,  G06F11/08

    CPC分类号： H04L1/0045 ,  G06F11/08 ,  G06F11/10 ,  H04L1/0061 ,  H04L2001/0094

    摘要： A system and method for detecting errors in high-speed asymmetric interfaces are described. Embodiments include transmitting digital data between a first system component and a second system component over a bidirectional interface, wherein the first component is significantly more intelligent than the second component. The first component receives a signature from the second component over a line of the interface concurrent with READ and WRITE operations over the interface. The latency associated with transmission of a signature from the second component to the first component is the time taken for the second component to compute a signature. The signature received is compared to a signature stored by the first component. Both signatures correspond to a particular READ or WRITE command. Based on the comparison, the first component determines whether the READ or WRITE operation was successful, and directs the second component as necessary.

    摘要翻译： 描述了用于检测高速非对称接口中的错误的系统和方法。 实施例包括通过双向接口在第一系统组件和第二系统组件之间传输数字数据，其中第一组件比第二组件明显更智能。 第一个组件通过接口的READ和WRITE操作同时从一个接口的一行接收第二个组件的签名。 与从第二组件到第一组件的签名传输相关联的延迟是第二组件计算签名所花费的时间。 所接收的签名与由第一组件存储的签名进行比较。 两个签名对应于特定的READ或WRITE命令。 基于比较，第一个组件确定READ或WRITE操作是否成功，并根据需要指示第二个组件。

    Error detection in high-speed asymmetric interfaces
    8.
    发明授权
    Error detection in high-speed asymmetric interfaces 有权
    高速非对称接口中的错误检测

    公开(公告)号：US07996731B2

    公开(公告)日：2011-08-09

    申请号：US11592074

    申请日：2006-11-01

    申请人： Joseph Macri ,  Stephen Morein ,  Claude Gauthier ,  Ming-Ju E. Lee ,  Lin Chen

    发明人： Joseph Macri ,  Stephen Morein ,  Claude Gauthier ,  Ming-Ju E. Lee ,  Lin Chen

    IPC分类号： G06F11/00

    CPC分类号： G06F11/10

    摘要： A system and method for detecting errors in high-speed asymmetric interfaces are described. Embodiments include transmitting digital data between a first system component and a second system component over a bidirectional interface, wherein the first component is significantly more intelligent than the second component. The first component controls many operations of the second component, including receiving a signature from the second component over an existing line of the interface. The signature received is compared to a signature stored by the first component. Both signatures correspond to a transaction over the interface. Based on the comparison, the first component determines whether the transaction was successful, and directs the second component as necessary.

    摘要翻译： 描述了用于检测高速非对称接口中的错误的系统和方法。 实施例包括通过双向接口在第一系统组件和第二系统组件之间传输数字数据，其中第一组件比第二组件明显更智能。 第一个组件控制第二个组件的许多操作，包括通过接口的现有行接收来自第二个组件的签名。 所接收的签名与由第一组件存储的签名进行比较。 两个签名对应于接口上的事务。 基于比较，第一个组件确定事务是否成功，并根据需要引导第二个组件。

    Fast transition from low-speed mode to high-speed mode in high-speed interfaces
    10.
    发明授权
    Fast transition from low-speed mode to high-speed mode in high-speed interfaces 有权
    在高速接口中从低速模式快速转换到高速模式

    公开(公告)号：US07752476B2

    公开(公告)日：2010-07-06

    申请号：US11804413

    申请日：2007-05-17

    申请人： Joseph Macri ,  Steven Morein ,  Ming-Ju E. Lee ,  Lin Chen

    发明人： Joseph Macri ,  Steven Morein ,  Ming-Ju E. Lee ,  Lin Chen

    IPC分类号： G01R31/28

    CPC分类号： G06F1/3275 ,  G06F1/3225 ,  G11C7/1045 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C2207/2227 ,  Y02D10/14

    摘要： Embodiments directed to a memory device and a memory controller that continue to operate in a low-power mode during the period required for analog timing circuitry to initialize and become usable, are described. During a low-speed to high-speed transition mode of operation for a high-speed interface, timing circuitry of the interface between the memory device and memory controller locks to a forward clock signal concurrent with the continued operation of the interface in low-speed mode. A reference clock signal configured to operate at a rate that provides both a high-speed mode and a low-speed mode and which is used as a single rate clock allows phase detection and correction circuitry to be disabled, thus allowing the idle period caused by a transition from low-speed mode to high-speed mode to be significantly reduced.

    摘要翻译： 描述了在模拟定时电路初始化和变得可用的时间段期间继续在低功率模式下工作的存储器件和存储器控制器的实施例。 在用于高速接口的低速到高速转换操作模式期间，存储器件和存储器控制器之间的接口的定时电路锁定到正向时钟信号，并且与低速接口的继续操作同时进行 模式。 参考时钟信号被配置为以提供高速模式和低速模式并且被用作单个速率时钟的速率操作，允许相位检测和校正电路被禁用，从而允许由 从低速模式向高速模式的转变将大大降低。