公开(公告)号：US08661300B1

公开(公告)日：2014-02-25

申请号：US13169977

申请日：2011-06-27

申请人： Joseph Macri ,  Stephen Morein ,  Claude Gauthier ,  Ming-Ju E. Lee ,  Lin Chen

发明人： Joseph Macri ,  Stephen Morein ,  Claude Gauthier ,  Ming-Ju E. Lee ,  Lin Chen

IPC分类号： G06F11/00

CPC分类号： G06F11/10

摘要： A system and method for detecting errors in high-speed asymmetric interfaces are described. Embodiments include transmitting digital data between a first system component and a second system component over a bidirectional interface, wherein the first component is significantly more intelligent than the second component. The first component controls many operations of the second component, including receiving a signature from the second component over an existing line of the interface. The signature received is compared to a signature stored by the first component. Both signatures correspond to a transaction over the interface. Based on the comparison, the first component determines whether the transaction was successful, and directs the second component as necessary.

摘要翻译： 描述了用于检测高速非对称接口中的错误的系统和方法。 实施例包括通过双向接口在第一系统组件和第二系统组件之间传输数字数据，其中第一组件比第二组件明显更智能。 第一个组件控制第二个组件的许多操作，包括通过接口的现有行接收来自第二个组件的签名。 所接收的签名与由第一组件存储的签名进行比较。 两个签名对应于接口上的事务。 基于比较，第一个组件确定事务是否成功，并根据需要引导第二个组件。

公开(公告)号：US08289056B2

公开(公告)日：2012-10-16

申请号：US12327787

申请日：2008-12-03

申请人： Min Xu ,  Ming-Ju E. Lee

发明人： Min Xu ,  Ming-Ju E. Lee

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  H03D13/004 ,  H03L7/089 ,  H03L7/0891

摘要： Embodiments include implementing a phase detector for a delay-locked loop (DLL) circuit that is operable to detect substantially 270 degree and substantially 540 degree phase differences between two clock signals. In an embodiment, a DLL circuit comprises a delay line receiving a system clock signal and generating a substantially 270 degree phase shifted clock signal and a substantially 540 degree phase shifted clock signal, a phase detector receiving the system clock signal and the substantially 270 degree phase shifted clock signal, and configured to generate corresponding up and down signals upon detection of a phase shift of substantially 270 degrees between the system clock signal and the substantially 270 degree phase shifted clock signal, a charge pump coupled to the phase detector, and configured to receive the up and down signals and generate a control signal responsive to thereto, and a regulator circuit to receive the control signal from the charge pump and generate a voltage control signal to the delay chain to control delay of the system clock signal.

摘要翻译： 实施例包括实现用于延迟锁定环路（DLL）电路的相位检测器，该电路可操作以检测两个时钟信号之间基本上270度和基本上540度的相位差。 在一个实施例中，DLL电路包括延迟线，其接收系统时钟信号并产生基本上270度的相移时钟信号和基本上540度的相移时钟信号，相位检测器接收系统时钟信号和基本270度相位 并且被配置为在检测到系统时钟信号和基本上270度的相移时钟信号之间基本上为270度的相移时产生相应的上下信号，耦合到相位检测器的电荷泵，并且被配置为 接收上升和下拉信号并响应于此产生控制信号，以及调节器电路，用于从电荷泵接收控制信号，并产生到延迟链的电压控制信号以控制系统时钟信号的延迟。

公开(公告)号：US08564347B2

公开(公告)日：2013-10-22

申请号：US13607045

申请日：2012-09-07

申请人： Min Xu ,  Ming-Ju E. Lee

发明人： Min Xu ,  Ming-Ju E. Lee

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  H03D13/004 ,  H03L7/089 ,  H03L7/0891

摘要： Embodiments include implementing a phase detector for a delay-locked loop (DLL) circuit that is operable to detect substantially 270 degree and substantially 540 degree phase differences between two clock signals. In an embodiment, a DLL circuit comprises a delay line receiving a system clock signal and generating phase shifted clock signals, a phase detector receiving the system clock signal and phase shifted clock signal, and configured to generate corresponding up and down signals upon detection of a phase shift of substantially 270 degrees between the system clock signal and the phase shifted clock signal, a charge pump coupled to the phase detector, and configured to receive the up and down signals and generate a control signal responsive to thereto, and a regulator circuit to receive the control signal from the charge pump and generate a voltage control signal to the delay chain to control delay of the system clock signal.

摘要翻译： 实施例包括实现用于延迟锁定环路（DLL）电路的相位检测器，该电路可操作以检测两个时钟信号之间基本上270度和基本上540度的相位差。 在一个实施例中，DLL电路包括接收系统时钟信号并产生相移时钟信号的延迟线，接收系统时钟信号和相移时钟信号的相位检测器，并且被配置为在检测到 在系统时钟信号和相移时钟信号之间基本为270度的相移，耦合到相位检测器的电荷泵，并且被配置为接收上升和下拉信号并响应于此产生控制信号，以及调节器电路 从电荷泵接收控制信号，并产生到延迟链的电压控制信号，以控制系统时钟信号的延迟。

公开(公告)号：US08429356B2

公开(公告)日：2013-04-23

申请号：US11359809

申请日：2006-02-22

申请人： Joseph D. Macri ,  Stephen Morein ,  Ming-Ju E. Lee ,  Lin Chen

发明人： Joseph D. Macri ,  Stephen Morein ,  Ming-Ju E. Lee ,  Lin Chen

IPC分类号： G06F13/00

CPC分类号： G06F12/00 ,  G06F13/4234 ,  G06F13/4243 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/1096

摘要： A method and system for performing byte-writes are described, where byte-writes involve writing only particular bytes of a multiple byte write operation. Embodiments include mask data that indicates which bytes are to be written in a byte-write operation. No dedicated mask pin(s) or dedicated mask line(s) are used. In one embodiment, the mask data is transmitted on data lines and store in response to a write_mask command. In one embodiment, the mask data is transmitted as part of the write command.

摘要翻译： 描述了用于执行字节写入的方法和系统，其中字节写入仅涉及仅写入多字节写入操作的特定字节。 实施例包括指示在字节写入操作中要写入哪些字节的掩码数据。 不使用专用的掩码引脚或专用掩码线。 在一个实施例中，掩码数据在数据线上传输，并响应于write_mask命令存储。 在一个实施例中，掩模数据作为写入命令的一部分被发送。

公开(公告)号：US07869525B2

公开(公告)日：2011-01-11

申请号：US11357291

申请日：2006-02-17

申请人： Joseph D. Macri ,  Stephen Morein ,  Ming-Ju E. Lee ,  Lin Chen

发明人： Joseph D. Macri ,  Stephen Morein ,  Ming-Ju E. Lee ,  Lin Chen

IPC分类号： H04B3/00

CPC分类号： H04L25/4915 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/0814 ,  H04L7/0004 ,  H04L7/0008 ,  H04L7/0037 ,  H04L7/0337

摘要： A dynamic bus inversion (DBI) method and system are described. In various embodiments, a transmitter transmits data over a multi-bit high-speed bus to a receiver. In an embodiment, the transmitter determines whether to invert the bus based on the number of data bits that will be transitioning to a new value. If it is determined that the bus is to be inverted, the transmitter encodes a DBI signal on a shared line of the bus. In an embodiment, the shared line is used for different purposes at different times, obviating the need for a dedicated line or pin for the encoded DBI signal. The receiver receives and decodes the DBI signal and, in response, appropriately decodes the received data.

摘要翻译： 描述了动态总线反演（DBI）方法和系统。 在各种实施例中，发射机通过多比特高速总线向接收机发送数据。 在一个实施例中，发射机基于将要转换到新值的数据比特数来确定是否反转总线。 如果确定总线被反相，则发送器对总线的共享线路上的DBI信号进行编码。 在一个实施例中，共享线路在不同时间用于不同的目的，从而避免了对编码的DBI信号的专用线路或引脚的需要。 接收器接收并解码DBI信号，作为响应，对接收到的数据进行适当的解码。

公开(公告)号：US20100134161A1

公开(公告)日：2010-06-03

申请号：US12327787

申请日：2008-12-03

申请人： Min Xu ,  Ming-Ju E. Lee

发明人： Min Xu ,  Ming-Ju E. Lee

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  H03D13/004 ,  H03L7/089 ,  H03L7/0891

摘要： Embodiments include implementing a phase detector for a delay-locked loop (DLL) circuit that is operable to detect substantially 270 degree and substantially 540 degree phase differences between two clock signals. In an embodiment, a DLL circuit comprises a delay line receiving a system clock signal and generating a substantially 270 degree phase shifted clock signal and a substantially 540 degree phase shifted clock signal, a phase detector receiving the system clock signal and the substantially 270 degree phase shifted clock signal, and configured to generate corresponding up and down signals upon detection of a phase shift of substantially 270 degrees between the system clock signal and the substantially 270 degree phase shifted clock signal, a charge pump coupled to the phase detector, and configured to receive the up and down signals and generate a control signal responsive to thereto, and a regulator circuit to receive the control signal from the charge pump and generate a voltage control signal to the delay chain to control delay of the system clock signal.

摘要翻译： 实施例包括实现用于延迟锁定环路（DLL）电路的相位检测器，该电路可操作以检测两个时钟信号之间基本上270度和基本上540度的相位差。 在一个实施例中，DLL电路包括延迟线，其接收系统时钟信号并产生基本上270度的相移时钟信号和基本上540度的相移时钟信号，相位检测器接收系统时钟信号和基本270度相位 并且被配置为在检测到系统时钟信号和基本上270度的相移时钟信号之间基本上为270度的相移时产生相应的上下信号，耦合到相位检测器的电荷泵，并且被配置为 接收上升和下拉信号并响应于此产生控制信号，以及调节器电路，用于从电荷泵接收控制信号，并产生到延迟链的电压控制信号以控制系统时钟信号的延迟。

公开(公告)号：US07663398B1

公开(公告)日：2010-02-16

申请号：US12273368

申请日：2008-11-18

申请人： Jaeseo Lee ,  Gin S. Yee ,  Ming-Ju E. Lee

发明人： Jaeseo Lee ,  Gin S. Yee ,  Ming-Ju E. Lee

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H04L25/0278 ,  H03K19/0005 ,  H04L25/0292

摘要： A circuit including control logic; and configurable impedance logic, operatively coupled to the control logic, comprising a configurable transistor structure operative to selectively change from a high impedance mode where the configurable transistor structure is configurable as a plurality of series connected diodes having their cathodes coupled together, and a low impedance mode where the configurable transistor structure is configurable to include a plurality of cascoded transistors. The circuit may further include at least one control signal line from the control logic to the configurable impedance logic, where the control signal line is operative to provide a control signal for configuring the configurable impedance logic.

摘要翻译： 包括控制逻辑的电路; 以及可操作地耦合到所述控制逻辑的可配置阻抗逻辑，包括可配置晶体管结构，其可操作以选择性地从高阻抗模式改变，其中所述可配置晶体管结构可配置为多个串联连接的二极管，其阴极耦合在一起，并且低阻抗 模式，其中可配置晶体管结构可配置为包括多个级联晶体管。 电路还可以包括从控制逻辑到可配置阻抗逻辑的至少一个控制信号线，其中控制信号线可操作以提供用于配置可配置阻抗逻辑的控制信号。

公开(公告)号：US20090125747A1

公开(公告)日：2009-05-14

申请号：US12356804

申请日：2009-01-21

申请人： Stephen Morein ,  Joseph Macri ,  Claude Gauthier ,  Ming-Ju E. Lee ,  Lin Chen

发明人： Stephen Morein ,  Joseph Macri ,  Claude Gauthier ,  Ming-Ju E. Lee ,  Lin Chen

IPC分类号： G06F1/12

CPC分类号： H04L7/02 ,  H04L7/0025 ,  H04L7/0091

摘要： An asymmetrical IO method and system are described. In one embodiment, a host device includes shared resources for data synchronization of the host device and a client device. The shared resources include a shared phase interpolator. In an embodiment, data lines between the host and client are also used to transmit phase information from the client device to the host device, obviating the need for additional, dedicated lines or pins.

摘要翻译： 描述了非对称IO方法和系统。 在一个实施例中，主机设备包括用于主机设备和客户端设备的数据同步的共享资源。 共享资源包括一个共享相位内插器。 在一个实施例中，主机和客户机之间的数据线也用于将相位信息从客户端设备发送到主机设备，从而避免了对额外的专用线或引脚的需要。

公开(公告)号：US07509515B2

公开(公告)日：2009-03-24

申请号：US11231193

申请日：2005-09-19

申请人： Joseph Macri ,  Steven Morein ,  Claude Gauthier ,  Ming-Ju E. Lee ,  Lin Chen

发明人： Joseph Macri ,  Steven Morein ,  Claude Gauthier ,  Ming-Ju E. Lee ,  Lin Chen

IPC分类号： G06F1/00

CPC分类号： G06F1/04 ,  G06F1/10 ,  H04L7/0012 ,  H04L7/033

摘要： A system and method for transmitting client phase information to a host device over a bidirectional data link is described. Embodiments include detecting a phase of a clock signal relative to a data signal transmitted between a host device and a client device over a bidirectional data link. The data link includes one or more data lines each configured to transmit a corresponding bit of the data signal. The phase is encoded as client phase information and transmitted between the host and client device over the one or more data lines. The client phase information is transmitted during an electrical turnaround time period of the bidirectional data link between a read and write operation over the data link.

摘要翻译： 描述了通过双向数据链路将客户端相位信息发送到主机设备的系统和方法。 实施例包括相对于通过双向数据链路在主机设备和客户端设备之间传输的数据信号检测时钟信号的相位。 数据链路包括一个或多个数据线，每个数据线被配置为传送数据信号的相应位。 该相位被编码为客户端相位信息，并通过一个或多个数据线在主机和客户端设备之间传输。 客户端相位信息是在数据链路上的读取和写入操作之间的双向数据链路的电气周转时间周期期间发送的。

公开(公告)号：US08892963B2

公开(公告)日：2014-11-18

申请号：US11595619

申请日：2006-11-09

申请人： Joseph Macri ,  Stephen Morein ,  Claude Gauthier ,  Ming-Ju E. Lee ,  Lin Chen

发明人： Joseph Macri ,  Stephen Morein ,  Claude Gauthier ,  Ming-Ju E. Lee ,  Lin Chen

IPC分类号： G06F11/00 ,  H04L1/00 ,  G06F11/10 ,  G06F11/08

CPC分类号： H04L1/0045 ,  G06F11/08 ,  G06F11/10 ,  H04L1/0061 ,  H04L2001/0094

摘要： A system and method for detecting errors in high-speed asymmetric interfaces are described. Embodiments include transmitting digital data between a first system component and a second system component over a bidirectional interface, wherein the first component is significantly more intelligent than the second component. The first component receives a signature from the second component over a line of the interface concurrent with READ and WRITE operations over the interface. The latency associated with transmission of a signature from the second component to the first component is the time taken for the second component to compute a signature. The signature received is compared to a signature stored by the first component. Both signatures correspond to a particular READ or WRITE command. Based on the comparison, the first component determines whether the READ or WRITE operation was successful, and directs the second component as necessary.

摘要翻译： 描述了用于检测高速非对称接口中的错误的系统和方法。 实施例包括通过双向接口在第一系统组件和第二系统组件之间传输数字数据，其中第一组件比第二组件明显更智能。 第一个组件通过接口的READ和WRITE操作同时从一个接口的一行接收第二个组件的签名。 与从第二组件到第一组件的签名传输相关联的延迟是第二组件计算签名所花费的时间。 所接收的签名与由第一组件存储的签名进行比较。 两个签名对应于特定的READ或WRITE命令。 基于比较，第一个组件确定READ或WRITE操作是否成功，并根据需要指示第二个组件。