公开(公告)号：US5086412A

公开(公告)日：1992-02-04

申请号：US616605

申请日：1990-11-21

申请人： James M. Jaffe ,  Norman E. Abt

发明人： James M. Jaffe ,  Norman E. Abt

IPC分类号： G11C11/22 ,  G11C14/00

CPC分类号： G11C11/22

摘要： A ferroelectric random access memory device contains columns of ferroelectric memory cells, each column of memory cells being coupled to a distinct bit line. Each memory cell is selectively coupled to a corresponding bit line by an access control transistor so that only one memory cell in the column is coupled to the bit line at a time. To read the data stored in a selected memory cell reads, the cell is strobed twice, separately sampling the output voltage generated each time. Since the first read is a destructive read, the second read operation always reads the cell in its "0" state. Then the two sampled outputs are compared, and if the first reading exceeds the second by at least a threshold amount then a "1" output value is generated. Otherwise a "0" is the output value. In a preferred embodiment, the time delay between strobing the memory cell and sampling its output is made longer the first time that the cell is read than for the second time that the cell is read. In this way, if the cell is storing a "0" bit, the first read will produce an output voltage that is smaller than it would have been had the first read not been delayed, which helps to ensure that cells storing "0" bit values are properly sensed.

公开(公告)号：US5236550A

公开(公告)日：1993-08-17

申请号：US874194

申请日：1992-04-24

申请人： Norman E. Abt ,  William H. Shepherd

发明人： Norman E. Abt ,  William H. Shepherd

IPC分类号： C23F4/00 ,  H01L21/3213

CPC分类号： H01L21/32136 ,  C23F4/00

摘要： The present invention provides a process for patterning ruthenium. A layer of ruthenium is formed on a substrate. The ruthenium is masked. The ruthenium is exposed to an oxygen plasma.

摘要翻译： 本发明提供了用于图案化钌的方法。 在基板上形成钌层。 钌被掩盖。 将钌暴露于氧等离子体。

公开(公告)号：US5543644A

公开(公告)日：1996-08-06

申请号：US410960

申请日：1995-03-27

申请人： Norman E. Abt ,  Reza Moazzami ,  Yoav Nissan-Cohen

发明人： Norman E. Abt ,  Reza Moazzami ,  Yoav Nissan-Cohen

IPC分类号： H01L21/02 ,  H01L27/115 ,  H01L29/78

CPC分类号： H01L27/11502 ,  H01L28/55 ,  H01L28/60

摘要： An electrical ceramic oxide capacitor utilizable in an integrated circuit memory device, and a method for making same is presented. A transistor is fabricated on a semiconductor substrate according to conventional techniques. A diffusion barrier is deposited over the transistor to protect it from subsequent process steps. Metal contacts are formed to contact the active transistor regions in the substrate, and additional barriers are formed to insulate the metal contacts. In a vertical embodiment, the barriers above the metal contacts can serve as bottom electrodes for the capacitor. In a lateral embodiment, the barriers on the side of the metal contacts serve as electrodes for the capacitor. Electrical ceramic oxide material is deposited between the electrode plates.

摘要翻译： 可以在集成电路存储器件中使用的电陶瓷氧化物电容器及其制造方法。 根据常规技术在半导体衬底上制造晶体管。 扩散阻挡层沉积在晶体管上以保护其免于随后的工艺步骤。 形成金属触点以接触衬底中的有源晶体管区域，并且形成附加的栅极以使金属触点绝缘。 在垂直实施例中，金属触点之上的屏障可以用作电容器的底部电极。 在横向实施例中，金属触头一侧的屏障用作电容器的电极。 电极陶瓷氧化物材料沉积在电极板之间。

公开(公告)号：US5401680A

公开(公告)日：1995-03-28

申请号：US837271

申请日：1992-02-18

申请人： Norman E. Abt ,  Reza Moazzami ,  Yoav Nissan-Cohen

发明人： Norman E. Abt ,  Reza Moazzami ,  Yoav Nissan-Cohen

IPC分类号： H01L21/02 ,  H01L27/115 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/11502 ,  H01L28/55 ,  H01L28/60

摘要： An electrical ceramic oxide capacitor utilizable in an integrated circuit memory device, and a method for making same is presented. A transistor is fabricated on a semiconductor substrate according to conventional techniques. A diffusion barrier is deposited over the transistor to protect it from subsequent process steps. Metal contacts are formed to contact the active transistor regions in the substrate, and additional barriers are formed to insulate the metal contacts. In a vertical embodiment, the barriers above the metal contacts can serve as bottom electrodes for the capacitor. In a lateral embodiment, the barriers on the side of the metal contacts serve as electrodes for the capacitor. Electrical ceramic oxide material is deposited between the electrode plates.

摘要翻译： 可以在集成电路存储器件中使用的电陶瓷氧化物电容器及其制造方法。 根据常规技术在半导体衬底上制造晶体管。 扩散阻挡层沉积在晶体管上以保护其免于随后的工艺步骤。 形成金属触点以接触衬底中的有源晶体管区域，并且形成附加的栅极以使金属触点绝缘。 在垂直实施例中，金属触点之上的屏障可以用作电容器的底部电极。 在横向实施例中，金属触头一侧的屏障用作电容器的电极。 电极陶瓷氧化物材料沉积在电极板之间。

公开(公告)号：US5354386A

公开(公告)日：1994-10-11

申请号：US328179

申请日：1989-03-24

申请人： David W. Cheung ,  Norman E. Abt ,  Peter A. McNally

发明人： David W. Cheung ,  Norman E. Abt ,  Peter A. McNally

IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/768 ,  H01L29/12 ,  H01L21/00 ,  H01L21/02

CPC分类号： H01L21/31116 ,  H01L21/76804

摘要： A multi-step plasma etch method for etching a tapered via having uniform bottom diameter ("CD") and extending through the resist and into the oxide layer of a coated semiconductor substrate, and a coated semiconductor substrate whose coating has been plasma etched to define such a tapered via. The first step of the inventive method is an anisotropic oxide plasma etch operation, preferably employing a plasma consisting primarily of CF.sub.4, which produces a non-tapered via having diameter substantially equal to CD and extending through the resist and into the oxide layer. A preferred embodiment of the inventive method includes a second step defining an upper sloping via portion without significantly increasing the diameter of a lower portion of the non-tapered via. This second step is a tapered resist plasma etch operation employing a mixture of oxygen (O.sub.2) and CF.sub.4. The slope of the upper sloping via portion may be controlled by varying the ratio of oxygen to CF.sub.4. In an alternative embodiment, the method produces a "stepped" via having an upper non-tapered portion which extends through the resist and has an opening diameter substantially greater than CD, and a lower non-tapered portion which extends through the oxide and has diameter substantially equal to CD.

摘要翻译： 一种用于蚀刻具有均匀底部直径（“CD”）并延伸穿过抗蚀剂并进入涂覆的半导体衬底的氧化物层的锥形通孔的多级等离子体蚀刻方法，以及涂覆半导体衬底，其涂层已被等离子体蚀刻以界定 这样的锥形通孔。 本发明方法的第一步是各向异性氧化物等离子体蚀刻操作，优选使用主要由CF4组成的等离子体，其产生直径基本上等于CD并延伸穿过抗蚀剂并进入氧化物层的非锥形通孔。 本发明方法的优选实施例包括限定上倾斜通孔部分的第二步骤，而不显着增加非锥形通孔的下部分的直径。 第二步是使用氧（O 2）和CF 4的混合物的锥形抗蚀剂等离子体蚀刻操作。 可以通过改变氧与CF 4的比例来控制上斜坡通孔部分的斜率。 在替代实施例中，该方法通过具有延伸穿过抗蚀剂并具有基本上大于CD的开口直径的上部非锥形部分产生“阶梯式”通道，以及延伸穿过氧化物的下部非锥形部分，并且具有直径 基本上等于CD。

公开(公告)号：US5889435A

公开(公告)日：1999-03-30

申请号：US884694

申请日：1997-06-30

申请人： Larry D. Smith ,  Norman E. Abt

发明人： Larry D. Smith ,  Norman E. Abt

IPC分类号： G01R29/26 ,  G01R31/30 ,  G01R31/317 ,  H03L7/081 ,  H03L7/085 ,  H03L7/087 ,  H03L7/06

CPC分类号： G01R31/31709 ,  G01R31/30 ,  H03L7/081 ,  H03L7/085 ,  H03L7/087 ,  G01R29/26

摘要： An ASIC includes a PLL and digital circuitry to quantize and measure phase and average maximum jitter between a system clock input to the PLL, and a PLL-generated clock signal. The system clock is input to a series-string of delay elements, each contributing a delay of about 1.DELTA.t. Each delay element is associated with a two-input logic element, such as an EX-OR gate or an EX-NOR gate. One input to each two-input logic element is a version of the PLL-generated clock delayed by about (N/2) .DELTA.t. The second input to the first EX-OR is the output from the first delay element, the second input to the first EX-NOR is the output from the second delay element, and so on. Whichever delay element outputs a signal most closely in phase with the delayed PLL-generated clock will have an associated two-input logic element signal with a minimum duty cycle. Each two-input logic element output signal is capacitor integrated, sampled, stored and digitized. The digitized output signal identifies the lowest duty cycle two-input logic element, and thus phase shift. The relative breadth of the integrated capacitor voltage profile provides a measure of average maximum jitter.

摘要翻译： ASIC包括PLL和数字电路，用于量化和测量输入到PLL的系统时钟与PLL生成的时钟信号之间的相位和平均最大抖动。 系统时钟输入到一系列延迟元件，每个延迟元件的延迟约为1 DELTA t。 每个延迟元件与诸如异或门或EX-NOR门的双输入逻辑元件相关联。 每个双输入逻辑元件的一个输入是延迟约（N / 2）DELTA t的PLL生成时钟的版本。 第一个EX-OR的第二个输入是第一个延迟元件的输出，第一个EX-NOR的第二个输入是第二个延迟元件的输出，依此类推。 无论哪个延迟元件输出与延迟PLL产生的时钟最相同的信号，将具有最小占空比的相关联的双输入逻辑元件信号。 每个双输入逻辑单元输出信号是电容集成，采样，存储和数字化。 数字化输出信号识别最低占空比双输入逻辑元件，从而识别相移。 集成电容电压曲线的相对宽度提供平均最大抖动的度量。

公开(公告)号：US5337279A

公开(公告)日：1994-08-09

申请号：US861212

申请日：1992-03-31

申请人： Anne K. Gregory ,  Michael P. Brassington ,  Shi-Qing Wang ,  Norman E. Abt

发明人： Anne K. Gregory ,  Michael P. Brassington ,  Shi-Qing Wang ,  Norman E. Abt

IPC分类号： G11C29/50 ,  G11C7/00 ,  G11C11/22

CPC分类号： G11C29/50 ,  G11C11/22

摘要： A screening process for ferroelectric memory devices that provides a greater degree of confidence in the mechanical and thermal stability of the ferroelectric material than prior art screening processes. A correspondingly higher degree of confidence in the reliability of the screened part results.

摘要翻译： 铁电存储器件的筛选方法，比现有技术的筛选方法提供了对铁电材料的机械和热稳定性更大程度的置信度。 对被筛选部件的可靠性的相对较高的置信度。

公开(公告)号：US5292402A

公开(公告)日：1994-03-08

申请号：US910951

申请日：1992-07-09

申请人： Norman E. Abt ,  Sheldon Aronowitz

发明人： Norman E. Abt ,  Sheldon Aronowitz

IPC分类号： H01L21/308 ,  H01L21/311 ,  H01L21/00

CPC分类号： H01L21/31111 ,  H01L21/3081 ,  Y10S148/106

摘要： Materials of the lead perovskite family PbZr.sub.x Ti.sub.1-x O.sub.3 have been discovered to be excellent masking materials in the etching of silicon and silicon-containing materials with chlorine and fluorine -based plasmas. Generally, materials of the lead perovskite family are suitable masking materials for any material that is etched in chlorine and fluorine -based plasmas.

摘要翻译： 已经发现铅钙钛矿族PbZrxTi1-xO3的材料在用氯和氟基等离子体蚀刻硅和含硅材料时是优异的掩蔽材料。 一般来说，铅钙钛矿族的材料对于在氯和氟基等离子体中蚀刻的任何材料都是合适的掩蔽材料。