公开(公告)号：US20240250057A1

公开(公告)日：2024-07-25

申请号：US18384389

申请日：2023-10-27

申请人： JMJ Korea Co., Ltd.

发明人： Yun Hwa CHOI

IPC分类号： H01L23/00 ,  H01L23/14 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L25/065

CPC分类号： H01L24/40 ,  H01L23/14 ,  H01L23/3107 ,  H01L23/3672 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/41 ,  H01L25/0655 ,  H01L2224/4005 ,  H01L2224/40225 ,  H01L2224/41051 ,  H01L2924/10251 ,  H01L2924/1203 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/181

摘要： Provided is a semiconductor package and a method of manufacturing the same, and more particularly, to a semiconductor package and a method of manufacturing the same in which stress applied while molding is efficiently dispersed by a three-dimensional clip structure so that structural reliability may be improved.

公开(公告)号：US20210358832A1

公开(公告)日：2021-11-18

申请号：US17147460

申请日：2021-01-13

申请人： JMJ Korea Co., Ltd.

发明人： Yun Hwa CHOI

IPC分类号： H01L23/433 ,  H01L23/498 ,  H01L23/367

摘要： Provided is a semiconductor package including: a first substrate comprising a specific pattern formed thereon to enable electrical connection; a second substrate, which is spaced apart from and faces the first substrate, comprising a specific pattern formed thereon to enable electrical connection; at least one semiconductor chip attached to the first substrate; at least one metal post formed in a non-vertical structure between the first substrate and the second substrate for dispersing a coefficient of thermal expansion (CTE) stress directly generated from the second substrate, wherein the metal post comprises one end attached on the at least one semiconductor chip, and the other end attached on the pattern of the first substrate or the second substrate; at least one terminal lead electrically connected to the first substrate or the second substrate; and a package housing covering the first and second substrates and exposing the terminal leads to the outside.

公开(公告)号：US20210057313A1

公开(公告)日：2021-02-25

申请号：US16912724

申请日：2020-06-26

申请人： JMJ Korea Co., Ltd.

发明人： Yun Hwa CHOI

IPC分类号： H01L23/495 ,  H01L23/31 ,  H01L23/367

摘要： Provided is a semiconductor package having an exposed heat sink for high thermal conductivity. The semiconductor package includes at least one semiconductor chip 110, the lead frame 120, a signal line 130, the sealing member 140, and at least one heat sink 150, wherein the lead frame 120 has a first surface, to which the semiconductor chips 110 are attached, and a second surface facing the first surface, the signal line 130 electrically connects the semiconductor chips 110 and the semiconductor chip 110 to the lead frame 120 by wire bonding or clip bonding, the sealing member 140 surrounds areas where the semiconductor chips 110 are attached, except for an external connection terminal 121 of the lead frame 120, and exposes the second surface of the lead frame 120, and the at least one heat sink 150 are attached to the second surface of the exposed lead frame 120. Here, spaces A and B are interposed between the sealing member 140 and the heat sink 150 which face each other, and the heat sink 150 is attached to the second surface of the lead frame 120 after molding of the sealing member 140. Accordingly, the sealing member 140 and the heat sink 150 may be prevented from being warped and thus, stress directly applied to the semiconductor chip 110 is removed. Therefore, reliability and electrical characteristics may be stably secured, and a terminal used in electrical connection may be easily secured through the lead frame 120 exposed to the outside of the sealing member 140.

公开(公告)号：US20240290700A1

公开(公告)日：2024-08-29

申请号：US18518359

申请日：2023-11-22

申请人： JMJ Korea Co., Ltd.

发明人： Yun Hwa CHOI

IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L23/14 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L23/49822 ,  H01L23/14 ,  H01L23/3121 ,  H01L23/49838 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29147 ,  H01L2224/32225 ,  H01L2224/48225 ,  H01L2224/73265 ,  H01L2924/181

摘要： Provided is a bonding substrate, a semiconductor package having a double-sided substrate, a method of manufacturing the bonding substrate, and a method of manufacturing the semiconductor package having a double-sided substrate, wherein the bonding substrate includes at least one upper substrate; at least one lower substrate which faces and is spaced apart from the upper substrate by a regular distance; and connecting members which comprises at least two layers formed of each different metal and is structurally or electrically ultrasonic bonded to the upper substrate or the lower substrate by using an ultrasonic bonding device. Accordingly, a tolerance for a vertically separated distance between upper and lower substrates may be minimized through ultrasonic bonding between the substrate and the connecting member and structural stress generated while molding may be reduced by using connecting members having each different Coefficient of Thermal Expansion (CTE).

公开(公告)号：US20230238297A1

公开(公告)日：2023-07-27

申请号：US18099921

申请日：2023-01-21

申请人： JMJ Korea Co., Ltd.

发明人： Yun Hwa CHOI

IPC分类号： H01L23/367 ,  H01L25/065 ,  H01L23/498 ,  H01L23/04 ,  H01L23/538 ,  H01L23/373 ,  H01L23/46 ,  H01L25/00

CPC分类号： H01L23/367 ,  H01L23/041 ,  H01L23/46 ,  H01L23/3735 ,  H01L23/5385 ,  H01L23/49811 ,  H01L25/50 ,  H01L25/0655

摘要： Provided is a semiconductor package and a method of manufacturing the same, wherein in the semiconductor package, an area on a surface of a heat release metal layer pressed by a molding die is expanded and the molding die directly and uniformly compresses an upper substrate and/or a lower substrate, each of which does not include heat release posts so that contamination of a substrate occurring due to a molding resin may be prevented and molding may be stably performed.

公开(公告)号：US20210335691A1

公开(公告)日：2021-10-28

申请号：US17237046

申请日：2021-04-22

申请人： JMJ Korea Co., Ltd.

发明人： Yun Hwa CHOI

IPC分类号： H01L23/367 ,  H01L25/07 ,  H01L23/00 ,  H01L23/373 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

摘要： Provided is a method of manufacturing a semiconductor having a double-sided substrate including preparing a first substrate on which a specific pattern is formed to enable electrical connection, preparing at least one semiconductor chip bonded to a metal post, bonding the at least one semiconductor chip to the first substrate, bonding a second substrate to the metal post, forming a package housing by packaging the first substrate and the second substrate to expose a lead frame, and forming terminal leads toward the outside of the package housing. Accordingly, the semiconductor chip and the metal post are previously joined to each other and are respectively bonded to the first substrate and the second substrate so that damage generated while bonding the semiconductor chip may be minimized and electrical properties and reliability of the semiconductor chip may be improved.

公开(公告)号：US20210249342A1

公开(公告)日：2021-08-12

申请号：US17105630

申请日：2020-11-27

申请人： JMJ Korea Co., Ltd.

发明人： Yun Hwa CHOI ,  Younghun KIM ,  Jeonghun CHO

IPC分类号： H01L23/495 ,  H01L23/498

摘要： The present invention provides a semiconductor package including: a lead frame comprising at least one terminal pad and at least one first terminal lead structurally connected to the terminal pads; at least one semiconductor chip attached to the upper surfaces of the terminal pads by using a conductive first adhesive; at least one heat radiation board attached to the lower surfaces of the terminal pads by using a second adhesive; at least one second terminal lead electrically connected to the semiconductor chips, spaced apart from the terminal pads at regular intervals, and separated from the heat radiation boards; and a package housing covering parts of the first and second terminal leads, the semiconductor chips, and the terminal pads.

公开(公告)号：US20210143076A1

公开(公告)日：2021-05-13

申请号：US16995825

申请日：2020-08-18

申请人： JMJ Korea Co., Ltd.

发明人： Yun Hwa CHOI ,  Young Hun KIM ,  Jeonghun CHO ,  So Young CHOI

IPC分类号： H01L23/367 ,  H01L23/373 ,  H01L25/07 ,  H01L23/00 ,  H01L21/48

摘要： A semiconductor package according to an embodiment of the present invention includes: a heat sink board including an insulated board and a first metal layer formed on the insulated board; at least one semiconductor chip placed on the first metal layer; a plurality of lead frames connected to the semiconductor chips used to electrically connect the semiconductor chips to the outside; and a package housing partially covering the heat sink board, wherein both end parts of the insulated board are projected further than both end parts of the first metal layer.

公开(公告)号：US20230282566A1

公开(公告)日：2023-09-07

申请号：US18074512

申请日：2022-12-05

申请人： JMJ Korea Co., Ltd.

发明人： Yun Hwa CHOI

IPC分类号： H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L23/40

CPC分类号： H01L23/49861 ,  H01L23/3121 ,  H01L23/3114 ,  H01L24/29 ,  H01L23/40

摘要： The present invention relates to a semiconductor package having a negative patterned substrate and a method of manufacturing the same, and more particularly, to a semiconductor package having a negative patterned substrate and a method of manufacturing the same, wherein in the semiconductor package and the method of manufacturing the same, a molding resin may not flow to the outside of the negative patterned substrate so as to prevent the substrate from being contaminated and a negative space is filled with the molding resin so as to stably perform a molding process.

公开(公告)号：US20220148998A1

公开(公告)日：2022-05-12

申请号：US17580598

申请日：2022-01-20

申请人： JMJ Korea Co., Ltd.

发明人： Yun Hwa CHOI ,  Jeonghun CHO ,  Young Hun KIM ,  Taeheon LEE

IPC分类号： H01L23/00 ,  H01L23/495 ,  H01L23/31

摘要： A semiconductor package according to an embodiment of the present invention Includes: a lead frame comprising a pad and a lead spaced apart from the pad by a regular interval; a semiconductor chip adhered on the pad; and a clip structure electrically connecting the semiconductor chip and the lead, wherein an one end of the clip structure connected to the semiconductor chip inclines with respect to upper surfaces of chip pads of the semiconductor chip and is adhered to the upper surfaces of the chip pads of the semiconductor chip. A semiconductor package according to another embodiment of the present invention includes: a semiconductor chip comprising one or more chip pads; one or more leads electrically connected to the chip pads; and a sealing member covering the semiconductor chip, wherein an one end of the lead inclines with respect to one surface of the chip pad and is adhered to the chip pad and an other end of the lead is exposed to the outside of the sealing member.