公开(公告)号：US11586462B2

公开(公告)日：2023-02-21

申请号：US16672081

申请日：2019-11-01

Applicant: International Business Machines Corporation

Inventor： Fadi Y. Busaba ,  Harold W. Cain, III ,  Michael Karl Gschwind ,  Valentina Salapura ,  Timothy J. Slegel

IPC: G06F12/00 ,  G06F9/46 ,  G06F13/16 ,  G06F13/42 ,  G06F3/06 ,  G06F12/0811 ,  G06F12/0817 ,  G06F12/0862

Abstract: A computer-implemented method includes identifying two or more memory locations and referencing, by a memory access request, the two or more memory locations. The memory access request is a single action pursuant to a memory protocol. The computer-implemented method further includes sending the memory access request from one or more processors to a node and fetching, by the node, data content from each of the two or more memory locations. The computer-implemented method further includes packaging, by the node, the data content from each of the two or more memory locations into a memory package, and returning the memory package from the node to the one or more processors. A corresponding computer program product and computer system are also disclosed.

公开(公告)号：US11275614B2

公开(公告)日：2022-03-15

申请号：US16586185

申请日：2019-09-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Harold W. Cain, III ,  Hubertus Franke ,  Charles R. Johns ,  Hung Q. Le ,  Ravi Nair ,  James A. Kahle

IPC: G06F9/50 ,  G06F9/30 ,  G06F9/38 ,  G06F9/455

Abstract: A computer system includes a processor, main memory, and controller. The processor includes a plurality of hardware threads configured to execute a plurality of software threads. The main memory includes a first register table configured to contain a current set of architected registers for the currently running software threads. The controller is configured to change a first number of the architected registers assigned to a given one of the software threads to a second number of architected registers when a result of monitoring current usage of the registers by the software threads indicates that the change will improve performance of the computer system. The processor includes a second register table configured to contain a subset of the architected registers and a mapping table for each software thread indicating whether the architected registers referenced by the corresponding software thread are located in the first register table or the second register table.

公开(公告)号：US10083076B2

公开(公告)日：2018-09-25

申请号：US15234081

申请日：2016-08-11

Applicant: International Business Machines Corporation

Inventor： Harold W. Cain, III ,  Michael Karl Gschwind ,  Maged M. Michael ,  Valentina Salapura ,  Chung-Lung K. Shum

IPC: G06F11/07 ,  G06F11/14 ,  G06F9/46 ,  G06F12/0815 ,  G06F12/084 ,  G06F9/30 ,  G06F12/0875

CPC classification number: G06F11/0793 ,  G06F9/30145 ,  G06F9/467 ,  G06F11/0721 ,  G06F11/0745 ,  G06F11/0751 ,  G06F11/0772 ,  G06F11/079 ,  G06F11/141 ,  G06F11/1474 ,  G06F12/0815 ,  G06F12/084 ,  G06F12/0875 ,  G06F2201/825 ,  G06F2212/1032 ,  G06F2212/452 ,  G06F2212/62 ,  G06F2212/621

Abstract: A transactional memory system salvages a hardware lock elision (HLE) transaction. A processor of the transactional memory system, based on a detection of a pending point-of-failure in a code region during HLE transactional execution, stops HLE transactional execution prior to the pending point-of-failure in the code region. The processor, based on information about a lock elided, commits a speculative state of the stopped HLE transactional execution that is stored, at least in part, in a gathering store cache. The processor starts non-transactional execution at the point of failure in the code region.

公开(公告)号：US09928158B2

公开(公告)日：2018-03-27

申请号：US15011557

申请日：2016-01-30

Applicant: International Business Machines Corporation

Inventor： Harold W. Cain, III ,  David M. Daly ,  Michael C. Huang ,  Kattamuri Ekanadham ,  Jose E. Moreira ,  Mauricio J. Serrano

IPC: G06F11/00 ,  G06F11/36 ,  G06F11/14

CPC classification number: G06F11/3636 ,  G06F11/1474 ,  G06F11/1492 ,  G06F11/1497 ,  G06F11/362 ,  G06F11/3648 ,  G06F11/3668 ,  G06F2201/865 ,  G06F2201/87

Abstract: A method for detecting a software-race condition in a program includes copying a state of a transaction of the program from a first core of a multi-core processor to at least one additional core of the multi-core processor, running the transaction, redundantly, on the first core and the at least one additional core given the state, outputting a result of the first core and the at least one additional core, and detecting a difference in the results between the first core and the at least one additional core, wherein the difference indicates the software-race condition.

公开(公告)号：US09817693B2

公开(公告)日：2017-11-14

申请号：US14212217

申请日：2014-03-14

Applicant: International Business Machines Corporation

Inventor： Fadi Y. Busaba ,  Harold W. Cain, III ,  Michael K. Gschwind ,  Christian Jacobi ,  Valentina Salapura ,  Eric M. Schwarz ,  Timothy J. Slegel

IPC: G06F12/0815 ,  G06F12/0817 ,  G06F9/46 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F9/466 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3859 ,  G06F12/0815 ,  G06F2212/621

Abstract: Embodiments relate to implementing a coherence protocol. An aspect includes sending a request for data to a remote processor and receiving by a processor a response from the remote processor. The response has a transaction status of a remote transaction on the remote processor. The processor adds the transaction status of the remote transaction on the remote processor in a local transaction interference tracking table.

公开(公告)号：US09753764B2

公开(公告)日：2017-09-05

申请号：US15240464

申请日：2016-08-18

Applicant: International Business Machines Corporation

Inventor： Fadi Y. Busaba ,  Harold W. Cain, III ,  Michael Karl Gschwind ,  Maged M. Michael ,  Valentina Salapura

IPC: G06F9/46 ,  G06F9/52 ,  G06F12/084 ,  G06F12/0875 ,  G06F11/14 ,  G06F9/50

CPC classification number: G06F9/467 ,  G06F9/5044 ,  G06F9/528 ,  G06F11/1405 ,  G06F11/1474 ,  G06F11/3037 ,  G06F11/3409 ,  G06F12/084 ,  G06F12/0875 ,  G06F2201/81 ,  G06F2212/314 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/621

Abstract: A transactional memory system determines whether to pass control of a transaction to an about-to-run-out-of-resource handler. A processor of the transactional memory system determines information about an about-to-run-out-of-resource handler for transaction execution of a code region of a hardware transaction. The processor dynamically monitors an amount of available resource for the currently running code region of the hardware transaction. The processor detects that the amount of available resource for transactional execution of the hardware transaction is below a predetermined threshold level. The processor, based on the detecting, saves speculative state information of the hardware transaction, and executes the about-to-run-out-of-resource handler, the about-to-run-out-of-resource handler determining whether the hardware transaction is to be aborted or salvaged.

公开(公告)号：US09710271B2

公开(公告)日：2017-07-18

申请号：US14318782

申请日：2014-06-30

Applicant: International Business Machines Corporation

Inventor： Fadi Y. Busaba ,  Harold W. Cain, III ,  Dan F. Greiner ,  Michael Karl Gschwind ,  Valentina Salapura ,  Eric M. Schwarz ,  Chung-Lung K. Shum

IPC: G06F9/30 ,  G06F9/46 ,  G06F12/08 ,  G06F13/16 ,  G06F11/34 ,  G06F12/084 ,  G06F12/0875

CPC classification number: G06F9/30098 ,  G06F9/467 ,  G06F11/3409 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0875 ,  G06F13/1663 ,  G06F2212/1024 ,  G06F2212/314 ,  G06F2212/452

Abstract: Execution of a transaction may be initiated by a CPU in a transactional execution (TX) environment. A set of TX performance characteristics of the transaction during the transactional execution may be collected and stored in a location specified by an instruction of the transaction when the transactional execution ends or aborts.

公开(公告)号：US09703560B2

公开(公告)日：2017-07-11

申请号：US14830872

申请日：2015-08-20

Applicant: International Business Machines Corporation

Inventor： Fadi Y. Busaba ,  Harold W. Cain, III ,  Dan F. Greiner ,  Michael Karl Gschwind ,  Valentina Salapura ,  Eric M. Schwarz ,  Chung-Lung K. Shum

IPC: G06F9/30 ,  G06F9/46 ,  G06F11/34 ,  G06F12/08 ,  G06F13/16 ,  G06F12/084 ,  G06F12/0875

CPC classification number: G06F9/30098 ,  G06F9/467 ,  G06F11/3409 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0875 ,  G06F13/1663 ,  G06F2212/1024 ,  G06F2212/314 ,  G06F2212/452

Abstract: Execution of a transaction may be initiated by a CPU in a transactional execution (TX) environment. A set of TX performance characteristics of the transaction during the transactional execution may be collected and stored in a location specified by an instruction of the transaction when the transactional execution ends or aborts.

公开(公告)号：US09619356B2

公开(公告)日：2017-04-11

申请号：US14963296

申请日：2015-12-09

Applicant: International Business Machines Corporation

Inventor： Harold W. Cain, III ,  David M. Daly ,  Kattamuri Ekanadham ,  Michael C. Huang ,  Jose E. Moreira ,  Mauricio J. Serrano

IPC: G06F11/273 ,  G06F11/16 ,  G06F11/22 ,  G06F11/26 ,  G06F11/263 ,  G06F11/18

CPC classification number: G06F11/273 ,  G06F11/1608 ,  G06F11/1629 ,  G06F11/18 ,  G06F11/181 ,  G06F11/2242 ,  G06F11/26 ,  G06F11/263

Abstract: A method for detecting errors in hardware including running a transaction on a plurality of cores, wherein each of the cores runs a respective copy of the transaction, periodically synchronizing the transaction on the cores throughout execution of the transaction, comparing results of the transaction on the cores, and determining an error in one or more of the cores.

公开(公告)号：US20160350174A1

公开(公告)日：2016-12-01

申请号：US15234081

申请日：2016-08-11

Applicant: International Business Machines Corporation

Inventor： Harold W. Cain, III ,  Michael Karl Gschwind ,  Maged M. Michael ,  Valentina Salapura ,  Chung-Lung K. Shum

IPC: G06F11/07 ,  G06F9/30 ,  G06F12/0875 ,  G06F12/084 ,  G06F12/0815

CPC classification number: G06F11/0793 ,  G06F9/30145 ,  G06F9/467 ,  G06F11/0721 ,  G06F11/0745 ,  G06F11/0751 ,  G06F11/0772 ,  G06F11/079 ,  G06F11/141 ,  G06F11/1474 ,  G06F12/0815 ,  G06F12/084 ,  G06F12/0875 ,  G06F2201/825 ,  G06F2212/1032 ,  G06F2212/452 ,  G06F2212/62 ,  G06F2212/621

Abstract: A transactional memory system salvages a hardware lock elision (HLE) transaction. A processor of the transactional memory system, based on a detection of a pending point-of-failure in a code region during HLE transactional execution, stops HLE transactional execution prior to the pending point-of-failure in the code region. The processor, based on information about a lock elided, commits a speculative state of the stopped HLE transactional execution that is stored, at least in part, in a gathering store cache. The processor starts non-transactional execution at the point of failure in the code region.

Abstract translation: 事务存储系统抢救硬件锁定（HLE）事务。 事务存储器系统的处理器基于在HLE事务执行期间对代码区域中的挂起故障点的检测，在代码区域中的挂起故障点之前停止HLE事务执行。 处理器基于关于锁的信息被消除，提供停止的HLE事务执行的推测状态，其至少部分地存储在收集存储高速缓存中。 处理器在代码区域的故障点处开始非事务性执行。