公开(公告)号：US11288208B2

公开(公告)日：2022-03-29

申请号：US16218118

申请日：2018-12-12

Applicant: International Business Machines Corporation

Inventor： Ravi Nair ,  Charles R. Johns ,  James A. Kahle ,  Changhoan Kim ,  Constantinos Evangelinos ,  Patrick D. Siegl

IPC: G06F12/1072 ,  G06F12/0817 ,  G06F12/02 ,  G06F9/54 ,  G06F12/1018 ,  G06F13/16 ,  G06F12/06

Abstract: An approach is described that provides access to a named data element in a Coordination Namespace that is stored in a memory that is distributed amongst a set of nodes. A request of a name corresponding to the named data element is received from a requesting process and the approach responsively searches for the name in the Coordination Namespace. In response to determining an absence of data corresponding to the named data element, a pending state is indicated to the requesting process. In response to determining that the data corresponding to the named data element exists, a successful state is returned to the requesting process. In one embodiment, the successful state also includes providing the requesting process with access to the data corresponding to the named data element.

公开(公告)号：US11275614B2

公开(公告)日：2022-03-15

申请号：US16586185

申请日：2019-09-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Harold W. Cain, III ,  Hubertus Franke ,  Charles R. Johns ,  Hung Q. Le ,  Ravi Nair ,  James A. Kahle

IPC: G06F9/50 ,  G06F9/30 ,  G06F9/38 ,  G06F9/455

Abstract: A computer system includes a processor, main memory, and controller. The processor includes a plurality of hardware threads configured to execute a plurality of software threads. The main memory includes a first register table configured to contain a current set of architected registers for the currently running software threads. The controller is configured to change a first number of the architected registers assigned to a given one of the software threads to a second number of architected registers when a result of monitoring current usage of the registers by the software threads indicates that the change will improve performance of the computer system. The processor includes a second register table configured to contain a subset of the architected registers and a mapping table for each software thread indicating whether the architected registers referenced by the corresponding software thread are located in the first register table or the second register table.

公开(公告)号：US11200168B2

公开(公告)日：2021-12-14

申请号：US16214597

申请日：2018-12-10

Applicant: International Business Machines Corporation

Inventor： Charles R. Johns ,  Jose R. Brunheroto

IPC: G06F12/0815 ,  G06F11/10

Abstract: An approach is disclosed that caches distant memories within the storage a local node. The approach provides a memory caching infrastructure that supports virtual addressing by utilizing memory in the local node as a cache of distant memories for data granules. The data granules are accessed along with metadata and an ECC associated with the data granule. The metadata is updated to indicate storage of the selected data granule in the cache.

公开(公告)号：US20200183859A1

公开(公告)日：2020-06-11

申请号：US16216863

申请日：2018-12-11

Applicant: International Business Machines Corporation

Inventor： Charles R. Johns ,  James A. Kahle ,  James C. Sexton ,  Ravi Nair

IPC: G06F12/1072 ,  G06F12/1009 ,  G06F12/06 ,  G06F12/109

Abstract: An approach is described that provides a distributed directory structure within a storage of an information handling system (a local node). A request is received with the request corresponding to a shared virtual address. The shared virtual address that is shared amongst a number of nodes that includes the local node and some remote nodes. A Global Address Space Directory (GASD) is retrieved that corresponds to a global virtual address space. The GASD is stored in a Coordination Namespace that is stored in a memory that is distributed amongst the nodes. A mapping that is included in the GASD is used to determine the node where the shared virtual address currently resides. The shared virtual address is then accessed from the node where it currently resides.

公开(公告)号：US20200183857A1

公开(公告)日：2020-06-11

申请号：US16215244

申请日：2018-12-10

Applicant: International Business Machines Corporation

Inventor： Ravi Nair ,  Charles R. Johns

IPC: G06F12/1018

Abstract: An approach is disclosed that locates a named data element by a local node. A name corresponding to the named data element is received, the named data element exists in a Coordination Namespace allocated in a memory area that is distributed amongst a set of nodes that include the local node and remote nodes. A predicted node identifier is received and then the named data element is requested from the predicted node based on the predicted node identifier.

公开(公告)号：US20220207191A1

公开(公告)日：2022-06-30

申请号：US17138552

申请日：2020-12-30

Applicant: International Business Machines Corporation

Inventor： Steven Robert Hetzler ,  Guerney D. H. Hunt ,  Charles R. Johns ,  James A. Kahle

IPC: G06F21/79 ,  G06F21/72 ,  G06F21/74 ,  G06F21/60

Abstract: A computer-implemented method includes, receiving, by a source node, a request from a destination node for data stored in a region of shared memory controlled by the source node. The data is encrypted in a local key of the source node. The method includes decrypting, by the source node, the locally encrypted data using the local key and encrypting, by the source node, the decrypted data using a first key for generating first encrypted data. The method also includes encrypting, by the source node, the first encrypted data using a second key for generating second encrypted data, and sending, by the source node, the second encrypted data to the destination node. A computer program product includes one or more computer readable storage media and program instructions collectively stored on the one or more computer readable storage media. The program instructions includes program instructions to perform the foregoing method.

公开(公告)号：US11016908B2

公开(公告)日：2021-05-25

申请号：US16216863

申请日：2018-12-11

Applicant: International Business Machines Corporation

Inventor： Charles R. Johns ,  James A. Kahle ,  James C. Sexton ,  Ravi Nair

IPC: G06F12/10 ,  G06F12/1072 ,  G06F12/1009 ,  G06F12/109 ,  G06F12/06

Abstract: An approach is described that provides a distributed directory structure within a storage of an information handling system (a local node). A request is received with the request corresponding to a shared virtual address. The shared virtual address that is shared amongst a number of nodes that includes the local node and some remote nodes. A Global Address Space Directory (GASD) is retrieved that corresponds to a global virtual address space. The GASD is stored in a Coordination Namespace that is stored in a memory that is distributed amongst the nodes. A mapping that is included in the GASD is used to determine the node where the shared virtual address currently resides. The shared virtual address is then accessed from the node where it currently resides.

公开(公告)号：US10831537B2

公开(公告)日：2020-11-10

申请号：US15435803

申请日：2017-02-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Harold W. Cain, III ,  Hubertus Franke ,  Charles R. Johns ,  Hung Q. Le ,  Ravi Nair

IPC: G06F9/50 ,  G06F9/30 ,  G06F9/38 ,  G06F9/455

Abstract: A computer system includes a processor, main memory, and controller. The processor includes a plurality of hardware threads configured to execute a plurality of software threads. The main memory includes a first register table configured to contain a current set of architected registers for the currently running software threads. The controller is configured to change a first number of the architected registers assigned to a given one of the software threads to a second number of architected registers when a result of monitoring current usage of the registers by the software threads indicates that the change will improve performance of the computer system. The processor includes a second register table configured to contain a subset of the architected registers and a mapping table for each software thread indicating whether the architected registers referenced by the corresponding software thread are located in the first register table or the second register table.

公开(公告)号：US20200183842A1

公开(公告)日：2020-06-11

申请号：US16214856

申请日：2018-12-10

Applicant: International Business Machines Corporation

Inventor： James A. Kahle ,  Charles R. Johns

IPC: G06F12/0817 ,  G06F12/084

Abstract: An approach is disclosed that tracks memory transactions by a node. The approach establishes a transaction processing state corresponding to common virtual addresses accessed by a processing threads. Transactions are executed by the threads. A selected transaction is allowed to complete. In response to detecting a conflict in the transaction processing state, completion of a non-selected transaction is inhibited.

公开(公告)号：US09483424B1

公开(公告)日：2016-11-01

申请号：US14960082

申请日：2015-12-04

Applicant: International Business Machines Corporation

Inventor： Charles R. Johns ,  Eric N. Lais ,  Jeffrey A. Stuecheli

IPC: G06F13/42 ,  G06F13/16

CPC classification number: G06F13/1673 ,  G06F13/4282 ,  G06F2213/0026

Abstract: Embodiments of the present disclosure use non-blocking writes (NBWs) to send high priority information (e.g., cache writebacks) on a designated channel that is separate from a channel used for other commands (e.g., normal memory write commands). By using NBWs and a designated channel to send cache writebacks, the cache writebacks will not be blocked by normal memory write commands. For example, an endpoint device may indicate that a TLP includes an NBW. Based on the indication, the root complex may send the NBWs on a dedicated NBW channel such that the NBW is not blocked by normal memory writes.

Abstract translation: 本公开的实施例使用非阻塞写（NBW）来在与用于其他命令（例如，正常存储器写命令）的信道分离的指定信道上发送高优先级信息（例如，高速缓存回写）。 通过使用NBW和指定的通道发送缓存回写，缓存回写不会被正常的内存写入命令阻止。 例如，端点设备可以指示TLP包括NBW。 根据指示，根复合体可以将NBW发送到专用NBW信道上，使得NBW不被正常存储器写入阻塞。