公开(公告)号：US10809790B2

公开(公告)日：2020-10-20

申请号：US15638573

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Yiftach Gilad ,  Ariel Szapiro ,  Elkana Korem ,  Alexander Gendler

IPC: G06F1/32 ,  G06F1/324 ,  G06F1/08 ,  G06F1/3296 ,  H03K5/133 ,  H03K19/003 ,  G11C29/02 ,  G11C7/22 ,  G11C5/14 ,  H03K5/00

Abstract: Apparatus and methods are provided for improving yield and frequency performance of integrated circuit processors, such as multiple-core processors. In an example, an apparatus can include a plurality of clock buffers, each clock buffer of the plurality of clock buffers configured to receive a first clock signal and distribute a plurality of second clock signals, a one-time programmable locate critical path mechanism configured provide a plurality of indications to enable or disable a delay of each clock buffer of the plurality of clock buffers, and a power management control circuit configured to over-ride one or more of the plurality of indications in a first non-test mode of operation of the apparatus and to not over-ride the one or more indications in a second non-test mode of operation of the apparatus.

公开(公告)号：US11544062B2

公开(公告)日：2023-01-03

申请号：US16833596

申请日：2020-03-28

Applicant: Intel Corporation

Inventor： Raanan Sade ,  Igor Yanover ,  Stanislav Shwartsman ,  Muhammad Taher ,  David Zysman ,  Liron Zur ,  Yiftach Gilad

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F9/50

Abstract: An apparatus and method for pairing store operations. For example, one embodiment of a processor comprises: a grouping eligibility checker to evaluate a plurality of store instructions based on a set of grouping rules to determine whether two or more of the plurality of store instructions are eligible for grouping; and a dispatcher to simultaneously dispatch a first group of store instructions of the plurality of store instructions determined to be eligible for grouping by the grouping eligibility checker.

公开(公告)号：US20160070651A1

公开(公告)日：2016-03-10

申请号：US14481266

申请日：2014-09-09

Applicant: Intel Corporation

Inventor： Stanislav Shwartsman ,  Robert S. Chappell ,  Ronak Singhal ,  Ryan L. Carlson ,  Raanan Sade ,  Omar M. Shaikh ,  Liron Zur ,  Yiftach Gilad

IPC: G06F12/08

CPC classification number: G06F12/0897 ,  G06F12/0862 ,  G06F2212/1021 ,  G06F2212/402 ,  G06F2212/602

Abstract: A processor includes a cache hierarchy and an execution unit. The cache hierarchy includes a lower level cache and a higher level cache. The execution unit includes logic to issue a memory operation to access the cache hierarchy. The lower level cache includes logic to determine that a requested cache line of the memory operation is unavailable in the lower level cache, determine that a line fill buffer of the lower level cache is full, and initiate prefetching of the requested cache line from the higher level cache based upon the determination that the line fill buffer of the lower level cache is full. The line fill buffer is to forward miss requests to the higher level cache.

Abstract translation: 处理器包括缓存层级和执行单元。 高速缓存层级包括较低级别的缓存和较高级别的高速缓存。 执行单元包括发出存储器操作以访问高速缓存层级的逻辑。 下级高速缓存包括确定存储器操作的所请求的高速缓存行在下级高速缓存中不可用的逻辑，确定较低级高速缓存的行填充缓冲区已满，并且从较高级缓存启动所请求的高速缓存行的预取 基于下级缓存的行填充缓冲器的确定已满的高级缓存。 行填充缓冲区是将错误请求转发到更高级别的缓存。

公开(公告)号：US20190004583A1

公开(公告)日：2019-01-03

申请号：US15638573

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Yiftach Gilad ,  Ariel Szapiro ,  Elkana Korem ,  Alexander Gendler

IPC: G06F1/32 ,  G06F1/08 ,  H03K5/133 ,  H03K19/003 ,  G11C7/22 ,  G11C5/14

Abstract: Apparatus and methods are provided for improving yield and frequency performance of integrated circuit processors, such as multiple-core processors. In an example, an apparatus can include a plurality of clock buffers, each clock buffer of the plurality of clock buffers configured to receive a first clock signal and distribute a plurality of second clock signals, a one-time programmable locate critical path mechanism configured provide a plurality of indications to enable or disable a delay of each clock buffer of the plurality of clock buffers, and a power management control circuit configured to over-ride one or more of the plurality of indications in a first non-test mode of operation of the apparatus and to not over-ride the one or more indications in a second non-test mode of operation of the apparatus.

公开(公告)号：US09558127B2

公开(公告)日：2017-01-31

申请号：US14481266

申请日：2014-09-09

Applicant: Intel Corporation

Inventor： Stanislav Shwartsman ,  Robert S. Chappell ,  Ronak Singhal ,  Ryan L. Carlson ,  Raanan Sade ,  Omar M. Shaikh ,  Liron Zur ,  Yiftach Gilad

IPC: G06F12/08

CPC classification number: G06F12/0897 ,  G06F12/0862 ,  G06F2212/1021 ,  G06F2212/402 ,  G06F2212/602

Abstract: A processor includes a cache hierarchy and an execution unit. The cache hierarchy includes a lower level cache and a higher level cache. The execution unit includes logic to issue a memory operation to access the cache hierarchy. The lower level cache includes logic to determine that a requested cache line of the memory operation is unavailable in the lower level cache, determine that a line fill buffer of the lower level cache is full, and initiate prefetching of the requested cache line from the higher level cache based upon the determination that the line fill buffer of the lower level cache is full. The line fill buffer is to forward miss requests to the higher level cache.

Abstract translation: 处理器包括缓存层级和执行单元。 高速缓存层级包括较低级别的缓存和较高级别的高速缓存。 执行单元包括发出存储器操作以访问高速缓存层级的逻辑。 下级高速缓存包括确定存储器操作的所请求的高速缓存行在下级高速缓存中不可用的逻辑，确定较低级高速缓存的行填充缓冲区已满，并且从较高级缓存启动所请求的高速缓存行的预取 基于下级缓存的行填充缓冲器的确定已满的高级缓存。 行填充缓冲区是将错误请求转发到更高级别的缓存。