公开(公告)号：US20230230923A1

公开(公告)日：2023-07-20

申请号：US17824974

申请日：2022-05-26

Applicant: Intel Corporation

Inventor： Gerald Pasdast ,  Zhiguo Qian ,  Sathya Narasimman Tiagaraj ,  Lakshmipriya Seshan ,  Peipei Wang ,  Debendra Das Sharma ,  Srikanth Nimmagadda ,  Zuoguo Wu ,  Swadesh Choudhary ,  Narasimha Lanka

IPC: H01L23/538 ,  H01L25/16 ,  H01L23/00

CPC classification number: H01L23/5382 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/16 ,  H01L2224/16225

Abstract: A microelectronic device, a semiconductor package including the device, an IC device assembly including the package, and a method of making the device. The device includes a substrate; physical layer (PHY) circuitry on the substrate including a plurality of receive (RX) circuits and a plurality of transmit (TX) circuits; electrical contact structures at a bottom surface of the device; signal routing paths extending between the electrical contact structures on one hand, and, on another hand, at least some of the RX circuits or at least some of the TX circuits; and electrical pathways leading to the PHY circuitry and configured such that at least one of: an enable signal input to the device is to travel through at least some of the electrical pathways to enable a portion of the PHY circuitry; or a disable signal input to the device is to travel through at least some of the electrical pathways to disable a corresponding portion of the PHY circuitry.

公开(公告)号：US20230197676A1

公开(公告)日：2023-06-22

申请号：US17557166

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Gerald S. Pasdast ,  Adel A. Elsherbini ,  Nevine Nassif ,  Carleton L. Molnar ,  Vivek Kumar Rajan ,  Peipei Wang ,  Shawna M. Liff ,  Tejpal Singh ,  Johanna M. Swan

IPC: H01L25/065 ,  H01L23/498

CPC classification number: H01L25/0652 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/49838

Abstract: A microelectronic assembly is provided, comprising: a first integrated circuit (IC) die having a first connection to a first serializer/deserializer (SERDES) circuit and a second connection to a second SERDES circuit; a second IC die having the first SERDES circuit; and a third IC die having the second SERDES circuit, in which the first IC die is in a first layer, the second IC die and the third IC die are in a second layer not coplanar with the first layer, the first layer and the second layer are coupled by interconnects having a pitch of less than 10 micrometers between adjacent ones of the interconnects, and the first SERDES circuit and the second SERDES circuit are coupled by a conductive pathway.

公开(公告)号：US20230197675A1

公开(公告)日：2023-06-22

申请号：US17552845

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Gerald S. Pasdast ,  Yidnekachew Mekonnen ,  Adel A. Elsherbini ,  Peipei Wang ,  Vivek Kumar Rajan ,  Georgios Dogiamis

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L23/481 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2924/37001

Abstract: Embodiments of the present disclosure provide a microelectronic assembly comprising: a first integrated circuit (IC) die, the first IC die comprising an input/output (IO) circuit; and a plurality of IC dies, the plurality of IC dies comprising a second IC die, the second IC die comprising a microcontroller circuit to control the IO circuit, wherein the first IC die and the plurality of IC dies are coupled with interconnects having a pitch of less than 10 micrometers between adjacent ones of the interconnects.

公开(公告)号：US20220327276A1

公开(公告)日：2022-10-13

申请号：US17844356

申请日：2022-06-20

Applicant: Intel Corporation

Inventor： Lakshmipriya Seshan ,  Gerald Pasdast ,  Peipei Wang ,  Narasimha Lanka ,  Swadesh Choudhary ,  Zuoguo Wu ,  Debendra Das Sharma

IPC: G06F30/398 ,  G06F30/347 ,  G06F30/392

Abstract: In one embodiment, an apparatus includes a first die comprising: a die-to-die adapter to communicate with protocol layer circuitry and physical layer circuitry, where the die-to-die adapter is to receive first information of a first interconnect protocol; and the physical layer circuitry coupled to the die-to-die adapter. The physical layer circuitry is configured to receive and output the first information to a second die via an interconnect and comprises: a first plurality of transmitters to transmit data via a first plurality of data lanes; and at least one redundant transmitter. The physical layer circuitry may be configured to remap a first data lane of the first plurality of data lanes to the at least one redundant transmitter. Other embodiments are described and claimed.

公开(公告)号：US12159840B2

公开(公告)日：2024-12-03

申请号：US16910023

申请日：2020-06-23

Applicant: Intel Corporation

Inventor： Zhiguo Qian ,  Gerald Pasdast ,  Juan Zeng ,  Peipei Wang ,  Ahmad Siddiqui ,  Lakshmipriya Seshan

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/538

Abstract: Embodiments disclosed herein include multi-die packages with interconnects between the dies. In an embodiment, an electronic package comprises a package substrate, and a first die over the package substrate. In an embodiment, the first die comprises a first IO bump map, where bumps of the first IO bump map have a first pitch. In an embodiment, the electronic package further comprises a second die over the package substrate. In an embodiment, the second die comprises a second IO bump map, where bumps of the second IO bump map have a second pitch that is different than the first pitch. In an embodiment, the electronic package further comprises interconnects between the first IO bump map and the second IO bump map.

公开(公告)号：US12100662B2

公开(公告)日：2024-09-24

申请号：US17127304

申请日：2020-12-18

Applicant: Intel Corporation

Inventor： Zhiguo Qian ,  Gerald Pasdast ,  Peipei Wang ,  Daniel Krueger ,  Edward Burton

IPC: H01L23/538 ,  H01L21/50 ,  H01L23/50 ,  H01L25/065

CPC classification number: H01L23/5381 ,  H01L21/50 ,  H01L23/50 ,  H01L23/5385 ,  H01L23/5386 ,  H01L25/0657

Abstract: An integrated circuit (IC) package, comprising a substrate that comprises a bridge die embedded within a dielectric. A first die comprising a first input/output (I/O) transmitter and a second die comprising a second I/O receiver and electrically coupled to the bridge die. A first signal trace and a first power conductor are within the bridge die. The first signal trace and the first power conductor are electrically coupled to the first I/O transmitter and the second I/O receiver. The first signal trace is to carry a digital signal and the first power conductor to provide a voltage for the second I/O receiver to read the digital signal.

公开(公告)号：US10686582B1

公开(公告)日：2020-06-16

申请号：US16285056

申请日：2019-02-25

Applicant: Intel Corporation

Inventor： Gerald Pasdast ,  Nasser A. Kurd ,  Peipei Wang ,  Yingyu Miao ,  Lakshmipriya Seshan ,  Ishaan S. Shah

IPC: H04L7/00 ,  H03L7/081 ,  H03L7/093 ,  H03K5/00 ,  G06F1/08 ,  G06F1/10 ,  G06F1/06 ,  H03K3/037

Abstract: An apparatus and method is provided that compensates for the supply droops to minimize strobe shifts and to regain eye margin. The apparatus includes a droop detector to detect voltage droops at one or more trip (or threshold) levels and these detected voltage droops are translated to a shift in clock phase setting. For example, propagation delay of a delay locked loop (DLL) and/or clock edge selection from a phase interpolator (PI) is adjusted according to the detected voltage droop levels to maintain a trained relationship between the sampling clock strobe and data eye. A lookup table is used to determine a PI code or a DLL propagation delay code corresponding to a voltage droop level.

公开(公告)号：US20220199537A1

公开(公告)日：2022-06-23

申请号：US17127304

申请日：2020-12-18

Applicant: Intel Corporation

Inventor： Zhiguo Qian ,  Gerald Pasdast ,  Peipei Wang ,  Daniel Krueger ,  Edward Burton

IPC: H01L23/538 ,  H01L23/50 ,  H01L25/065 ,  H01L21/50

Abstract: An integrated circuit (IC) package, comprising a substrate that comprises a bridge die embedded within a dielectric. A first die comprising a first input/output (I/O) transmitter and a second die comprising a second I/O receiver and electrically coupled to the bridge die. A first signal trace and a first power conductor are within the bridge die. The first signal trace and the first power conductor are electrically coupled to the first I/O transmitter and the second I/O receiver. The first signal trace is to carry a digital signal and the first power conductor to provide a voltage for the second I/O receiver to read the digital signal.

公开(公告)号：US20230245999A1

公开(公告)日：2023-08-03

申请号：US17588392

申请日：2022-01-31

Applicant: Intel Corporation

Inventor： Gerald S. Pasdast ,  Peipei Wang ,  Adel A. Elsherbini

IPC: H01L25/065 ,  H01L23/538 ,  H04B3/02

CPC classification number: H01L25/0652 ,  H01L23/5383 ,  H01L23/5386 ,  H04B3/02

Abstract: Embodiments of the present disclosure provide a microelectronic assembly comprising: a first integrated circuit (IC) die in a first layer; an interposer in a second layer not coplanar with the first layer, the first layer coupled to the second layer by interconnects having a pitch of less than 10 micrometers between adjacent interconnects; and a first conductive pathway and a second conductive pathway in the interposer coupling the first IC die and a second IC die. The first IC die is configured to transmit at a first supply voltage through the first conductive pathway to a second IC die, the second IC die is configured to transmit to the first IC die through the second conductive pathway at a second supply voltage simultaneously with the first die transmitting at the first supply voltage, and the first supply voltage is different from the second supply voltage.