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公开(公告)号：US20240007087A1
公开(公告)日：2024-01-04
申请号：US17856887
申请日：2022-07-01
申请人： Intel Corporation
发明人： Steven Hsu , Amit Agarwal , Simeon Realov , Mark Anders , Ram Krishnamurthy
摘要： Techniques and mechanisms for an integrated clock gate (ICG) to selectively output a clock signal, and to provide frequency division functionality. In an embodiment, an ICG circuit comprises first circuitry which is coupled to receive a first clock signal, and second circuitry which is coupled to receive a control signal. The first circuitry provides a single edge triggered flip-flop functionality, and is coupled to communicate a feedback signal which the first circuitry is further coupled to receive. Based on the control signal and the feedback signal, the second circuitry performs an exclusive OR (XOR) operation to selectively enable the first circuitry to generate a second clock signal based on the first clock signal. In another embodiment, a frequency of the second clock signal is substantially equal to one half of a frequency of the first clock signal.
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2.发明授权公开(公告)号：US11288040B2
公开(公告)日：2022-03-29
申请号：US16435048
申请日：2019-06-07
申请人： Intel Corporation
发明人： Himanshu Kaul , Mark Anders
摘要： Systems, apparatuses and methods may provide for technology that conduct a first alignment between a plurality of floating-point numbers based on a first subset of exponent bits. The technology may also conduct, at least partially in parallel with the first alignment, a second alignment between the plurality of floating-point numbers based on a second subset of exponent bits, where the first subset of exponent bits are LSBs and the second subset of exponent bits are MSBs. In one example, technology adds the aligned plurality of floating-point numbers to one another. With regard to the second alignment, the technology may also identify individual exponents of a plurality of floating-point numbers, identify a maximum exponent across the individual exponents, and conduct a subtraction of the individual exponents from the maximum exponent, where the subtraction is conducted from MSB to LSB.
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3.发明申请公开(公告)号：US20190294415A1
公开(公告)日：2019-09-26
申请号：US16435048
申请日：2019-06-07
申请人： Intel Corporation
发明人： Himanshu Kaul , Mark Anders
摘要： Systems, apparatuses and methods may provide for technology that conduct a first alignment between a plurality of floating-point numbers based on a first subset of exponent bits. The technology may also conduct, at least partially in parallel with the first alignment, a second alignment between the plurality of floating-point numbers based on a second subset of exponent bits, where the first subset of exponent bits are LSBs and the second subset of exponent bits are MSBs. In one example, technology adds the aligned plurality of floating-point numbers to one another. With regard to the second alignment, the technology may also identify individual exponents of a plurality of floating-point numbers, identify a maximum exponent across the individual exponents, and conduct a subtraction of the individual exponents from the maximum exponent, where the subtraction is conducted from MSB to LSB.
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公开(公告)号：US20230376274A1
公开(公告)日：2023-11-23
申请号：US18362529
申请日：2023-07-31
申请人： Intel Corporation
发明人： Mark Anders , Arnab Raha , Amit Agarwal , Steven Hsu , Deepak Abraham Mathaikutty , Ram K. Krishnamurthy , Martin Power
CPC分类号： G06F7/5443 , G06F7/4876 , G06F7/485 , G06F5/012
摘要： A fused dot-product multiply-accumulate (MAC) circuit may support variable precisions of floating-point data elements to perform computations (e.g., MAC operations) in deep learning operations. An operation mode of the circuit may be selected based on the precision of an input element. The operation mode may be a FP16 mode or a FP8 mode. In the FP8 mode, product exponents may be computed based on exponents of floating-point input elements. A maximum exponent may be selected from the one or more product exponents. A global maximum exponent may be selected from a plurality of maximum exponents. A product mantissa may be computed and aligned with another product mantissa based on a difference between the global maximum exponent and a corresponding maximum exponent. An adder tree may accumulate the aligned product mantissas and compute a partial sum mantissa. The partial sum mantissa may be normalized using the global maximum exponent.
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公开(公告)号：US10374793B2
公开(公告)日：2019-08-06
申请号：US15374700
申请日：2016-12-09
申请人： Intel Corporation
发明人： Himanshu Kaul , Sanu Mathew , Mark Anders , Jesse Walker , Jason Sandri
摘要： An instruction and logic for a Simon-based hashing for validation are described. In one embodiment, a processor comprises: a memory the memory to store a plurality of values; and a hash circuit comprising a Simon cipher circuit operable to receive the plurality of values from the memory, to apply a Simon cipher, and to generate an output for each of the plurality of values; and circuitry coupled to the Simon cipher circuit to combine outputs from the Simon cipher circuit for each value of the plurality of values into a hash digest that is indicative of whether the values in the memory are valid.
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6.发明申请公开(公告)号：US20190042252A1
公开(公告)日：2019-02-07
申请号：US16147691
申请日：2018-09-29
申请人： Intel Corporation
发明人： Himanshu Kaul , Mark Anders , Seongjong Kim
摘要： A configurable integrated circuit to compute vector dot products between a first N-bit vector and a second N-bit vector in a plurality of precision modes. An embodiment includes M slices, each of which calculates the vector dot products between a corresponding segment of the first and the second N-bit vectors. Each of the slices outputs intermediary multiplier results for the lower precision modes, but not for highest precision mode. A plurality of adder trees to sum up the plurality of intermediate multiplier results, with each adder tree producing a respective adder out result. An accumulator to merge the adder out result from a first adder tree with the adder out result from a second adder tree to produce the vector dot product of the first and the second N-bit vector in the highest precision mode.
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公开(公告)号：US09843441B2
公开(公告)日：2017-12-12
申请号：US14035508
申请日：2013-09-24
申请人： Intel Corporation
发明人： Sanu Mathew , Vikram Suresh , Sudhir Satpathy , Mark Anders , Himanshu Kaul , Ram Krishnamurthy
CPC分类号： H04L9/0631 , H04L2209/24
摘要： Embodiments of an invention for a compact, low power Advanced Encryption Standard circuit are disclosed. In one embodiment, an apparatus includes an encryption unit having a substitution box and an accumulator. The substitution box is to perform a substitution operation on one byte per clock cycle. The accumulator is to accumulate four bytes and perform a mix-column operation in four clock cycles. The encryption unit is implemented using optimum Galois Field polynomial arithmetic for minimum area.
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公开(公告)号：US20230395506A1
公开(公告)日：2023-12-07
申请号：US17833708
申请日：2022-06-06
申请人： Intel Corporation
发明人： Miriam Reshotko , Elijah Karpov , Mark Anders , Gauri Auluck , Shakuntala Sundararajan , Michael Makowski , Caleb Barrett
IPC分类号： H01L23/532 , H01L23/522 , H01L21/768
CPC分类号： H01L23/53238 , H01L23/5226 , H01L21/76843 , H01L21/76877 , H01L23/53266
摘要： Adjacent interconnect features are in staggered, vertically spaced positions, which accordingly reduces their capacitive coupling within a level of interconnect metallization. Adjacent interconnect features may comprise a plurality of first interconnect lines with spaces therebetween. A dielectric material is over the first interconnect lines and within the spaces between the first interconnect lines. Resultant topography in the dielectric material defines a plurality of trenches between the first interconnect lines. The adjacent interconnect features further comprise a plurality of second interconnect lines interdigitated with the first interconnect lines that occupy at least a portion of the trenches between individual ones of the first interconnect lines.
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