- 专利标题: SELF-ALIGNED STAGGERED INTEGRATED CIRCUIT INTERCONNECT FEATURES
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申请号: US17833708申请日: 2022-06-06
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公开(公告)号: US20230395506A1公开(公告)日: 2023-12-07
- 发明人: Miriam Reshotko , Elijah Karpov , Mark Anders , Gauri Auluck , Shakuntala Sundararajan , Michael Makowski , Caleb Barrett
- 申请人: Intel Corporation
- 申请人地址: US CA nta Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 主分类号: H01L23/532
- IPC分类号: H01L23/532 ; H01L23/522 ; H01L21/768
摘要:
Adjacent interconnect features are in staggered, vertically spaced positions, which accordingly reduces their capacitive coupling within a level of interconnect metallization. Adjacent interconnect features may comprise a plurality of first interconnect lines with spaces therebetween. A dielectric material is over the first interconnect lines and within the spaces between the first interconnect lines. Resultant topography in the dielectric material defines a plurality of trenches between the first interconnect lines. The adjacent interconnect features further comprise a plurality of second interconnect lines interdigitated with the first interconnect lines that occupy at least a portion of the trenches between individual ones of the first interconnect lines.
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