公开(公告)号：US20200058761A1

公开(公告)日：2020-02-20

申请号：US16342865

申请日：2016-12-02

Applicant: Intel Corporation

Inventor： Byron HO ,  Michael L. HATTENDORF ,  Jeanne L. LUCE ,  Ebony L. MAYS ,  Erica J. THOMPSON

IPC: H01L29/66 ,  H01L21/768 ,  H01L29/78 ,  H01L29/08 ,  H01L27/092 ,  H01L21/8234 ,  H01L21/762

Abstract: Semiconductor devices having fin-end stress-inducing features, and methods of fabricating semiconductor devices having fin-end stress-inducing features, are described. In an example, a semiconductor structure includes a semiconductor fin protruding through a trench isolation region above a substrate. The semiconductor fin has a top surface, a first end, a second end, and a pair of sidewalls between the first end and the second end. A gate electrode is over a region of the top surface and laterally adjacent to a region of the pair of sidewalls of the semiconductor fin. The gate electrode is between the first end and the second end of the semiconductor fin. A first dielectric plug is at the first end of the semiconductor fin. A second dielectric plug is at the second end of the semiconductor fin.

公开(公告)号：US20200098626A1

公开(公告)日：2020-03-26

申请号：US16139241

申请日：2018-09-24

Applicant: Intel Corporation

Inventor： Shaestagir CHOWDHURY ,  Sirikarn SURAWANVIJIT ,  Biswadeep SAHA ,  Erica J. THOMPSON

IPC: H01L21/768 ,  H01L21/3213 ,  H01L23/522 ,  H01L23/532 ,  C22C19/03 ,  C22C19/07

Abstract: An integrated circuit structure comprises a dielectric layer on a substrate. An open structure is in the dielectric layer, and a void-free metal-alloy interconnect is formed in the open structure, wherein the void-free metal-alloy interconnect comprise a metal-alloy comprising a combination of two or more metallic elements excluding any mixing effects of a seed layer or liner deposited in the open structure prior to a metal fill material, and excluding effects of any doping material on the metal fill material.

公开(公告)号：US20200279941A1

公开(公告)日：2020-09-03

申请号：US16650834

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Cheng-Ying HUANG ,  Willy RACHMADY ,  Gilbert DEWEY ,  Erica J. THOMPSON ,  Aaron D. LILAK ,  Jack T. KAVALIEROS

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/165

Abstract: Disclosed are etchstop regions in fins of semiconductor devices, and related methods. A semiconductor device includes a buried region, a fin on the buried region, and a gate formed at least partially around the fin. At least a portion of the fin that borders the buried region includes an etchstop material. The etchstop material includes a doped semiconductor material that has a slower etch rate than that of an intrinsic form of the semiconductor material. A method of manufacturing a semiconductor device includes forming a gate on a fin, implanting part of the fin with dopants configured to decrease an etch rate of the part of the fin, removing at least part of the fin, and forming an epitaxial semiconductor material on a remaining proximal portion of the fin.

公开(公告)号：US20240096896A1

公开(公告)日：2024-03-21

申请号：US18523637

申请日：2023-11-29

Applicant: Intel Corporation

Inventor： Jun Sung KANG ,  Kai Loon CHEONG ,  Erica J. THOMPSON ,  Biswajeet GUHA ,  William HSU ,  Dax M. CRUM ,  Tahir GHANI ,  Bruce BEATTIE

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/161 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L29/0673 ,  H01L29/161 ,  H01L29/4236 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: Non-planar integrated circuit structures having mitigated source or drain etch from replacement gate process are described. For example, an integrated circuit structure includes a fin or nanowire. A gate stack is over the fin or nanowire. The gate stack includes a gate dielectric and a gate electrode. A first dielectric spacer is along a first side of the gate stack, and a second dielectric spacer is along a second side of the gate stack. The first and second dielectric spacers are over at least a portion of the fin or nanowire. An insulating material is vertically between and in contact with the portion of the fin or nanowire and the first and second dielectric spacers. A first epitaxial source or drain structure is at the first side of the gate stack, and a second epitaxial source or drain structure is at the second side of the gate stack.

公开(公告)号：US20240088296A1

公开(公告)日：2024-03-14

申请号：US18514974

申请日：2023-11-20

Applicant: Intel Corporation

Inventor： Erica J. THOMPSON ,  Aditya Kasukurti ,  Jun Sung Kang ,  Kai Loon Cheong ,  Biswajeet Guha ,  William Hsu ,  Bruce Beattie

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/7853 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/6653 ,  H01L29/6681 ,  H01L29/66818 ,  H01L29/7855 ,  H01L21/02238

Abstract: A nanowire device includes one or more nanowire having a first end portion, a second end portion, and a body portion between the first end portion and the second end portion. A first conductive structure is in contact with the first end portion and a second conductive structure is in contact with the second end portion. The body portion of the nanowire has a first cross-sectional shape and the first end portion has a second cross-sectional shape different from the first cross-sectional shape. Integrated circuits including the nanowire device and a method of cleaning a semiconductor structure are also disclosed.