公开(公告)号：US20190206781A1

公开(公告)日：2019-07-04

申请号：US15859309

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Aleksandar ALEKSOV ,  Kristof DARMAWIKARTA ,  Haobo CHEN ,  Changhua LIU ,  Sri Ranga Sai BOYAPATI ,  Bai NIE

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L23/49822

Abstract: Apparatuses, systems and methods associated with package substrate design with variable height conductive elements within a single layer are disclosed herein. In embodiments, a substrate may include a first layer, wherein a trench is located in the first layer, and a second layer located on a surface of the first layer. The substrate may further include a first conductive element located in a first portion of the second layer adjacent to the trench, wherein the first conductive element extends to fill the trench, and a second conductive element located in a second portion of the second layer, wherein the second conductive element is located on the surface of the first layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20240184209A1

公开(公告)日：2024-06-06

申请号：US18060593

申请日：2022-12-01

Applicant: Intel Corporation

Inventor： Changhua LIU ,  Bai NIE ,  Robert MAY

IPC: G03F7/20 ,  G03F7/00

CPC classification number: G03F7/201 ,  G03F7/0007 ,  G03F7/2006 ,  G03F7/2014

Abstract: The present disclosure is directed to a lithographic patterning system including a stage for supporting a substrate with a photo-definable polymer layer, a first actinic radiation source, which is configured to propagate light along a first optical axis, a first mask for patterning the propagated light from the first actinic radiation source, a second actinic radiation source, which is configured to propagate light along a second optical axis, and a second mask for patterning the propagated light from the second actinic radiation source. In a method, first and second propagated lights form an intersection in the photo-definable polymer layer, and a patterned semiconductor component is formed at the intersection.

公开(公告)号：US20210318612A1

公开(公告)日：2021-10-14

申请号：US17356536

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Hongxia FENG ,  Changhua LIU ,  Bohan SHAN ,  Dingying XU ,  Leonel ARANA ,  Manuel GADOGBE ,  Matthew TINGEY ,  Julianne TROIANO

IPC: G03F7/038 ,  G03F7/20 ,  G03F7/32

Abstract: The present disclosure is directed to a patterning process that includes providing a composite dry film resist on a surface, in which the composite dry film resist includes a base film, a barrier layer and a resist layer, in which the base film is disposed over the barrier layer and the barrier layer is disposed over the resist layer. In another aspect, the patterning process includes removing the base film from the barrier layer and exposing the barrier layer to form an exposure precursor, which has a first area and a second area, further exposing the first area of the exposure precursor to electromagnetic irradiation, which passes through the barrier layer and the resist layer in the exposed first area becomes water-insoluble, and removing the barrier layer and the unexposed second area to form a pattern template.

公开(公告)号：US20200064738A1

公开(公告)日：2020-02-27

申请号：US16111056

申请日：2018-08-23

Applicant: Intel Corporation

Inventor： Changhua LIU ,  Allan KETELSEN

IPC: G03F7/20 ,  H01L21/027

Abstract: Embodiments disclosed herein include a lithographic patterning system and methods of using such a system to form a microelectronic device. In an embodiment, the lithographic patterning system includes an actinic radiation source, a stage where a major surface of the stage is for supporting a substrate with a resist layer, and a first prism over the stage, where the first prism comprises a first face that is substantially parallel to the major surface of the stage. In an embodiment, the lithographic patterning system further comprises a second prism, where the second prism comprises a first surface that is substantially parallel to a second surface of the first prism, and where a second surface of the second prism has a reflective coating.

公开(公告)号：US20230027030A1

公开(公告)日：2023-01-26

申请号：US17958296

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Changhua LIU ,  Xiaoying GUO ,  Aleksandar ALEKSOV ,  Steve S. CHO ,  Leonel ARANA ,  Robert MAY ,  Gang DUAN

IPC: H01L23/00

Abstract: A patch structure of an integrated circuit package comprises a core having a first side facing downwards and a second side facing upwards. A first solder resist (SR) layer is formed on the first side of the core, wherein the first SR layer comprises a first layer interconnect (FLI) and has a first set of one or more microbumps thereon to bond to one or more logic die. A second solder resist (SR) layer is formed on the second side of the core, wherein the second SR layer has a second set of one or more microbumps thereon to bond with a substrate. One or more bridge dies includes a respective sets of bumps, wherein the one or more bridge dies is disposed flipped over within the core such that the respective sets of bumps face downward and connect to the first set of one or more microbumps in the FLI.

公开(公告)号：US20190169020A1

公开(公告)日：2019-06-06

申请号：US15832223

申请日：2017-12-05

Applicant: Intel Corporation

Inventor： Aleksandar ALEKSOV ,  Kristof DARMAWIKARTA ,  Robert A. MAY ,  Changhua LIU ,  Hiroki TANAKA ,  Feras EID

IPC: B81B7/02 ,  B81C1/00 ,  H01L23/498

Abstract: A package substrate is provided which comprises: one or more first conductive contacts on a first surface; one or more second conductive contacts on a second surface opposite the first surface; a dielectric layer between the first and the second surfaces; and an embedded sensing or actuating element on the dielectric layer conductively coupled with one of the first conductive contacts, wherein the embedded sensing or actuating element comprises a fixed metal layer in the dielectric layer and a flexible metal layer suspended over the fixed metal layer by one or more metal supports on the dielectric layer. Other embodiments are also disclosed and claimed.

公开(公告)号：US20230236517A1

公开(公告)日：2023-07-27

申请号：US18130328

申请日：2023-04-03

Applicant: Intel Corporation

Inventor： Changhua LIU ,  Jianyong MO ,  Liang ZHANG

IPC: G03F7/20 ,  B81B1/00 ,  B81C1/00

CPC classification number: G03F7/70733 ,  B81B1/00 ,  B81C1/00111 ,  G03F7/201 ,  B81B2203/0361 ,  B81C2201/0159

Abstract: Embodiments disclosed herein include lithographic patterning systems for non-orthogonal patterning and devices formed with such patterning. In an embodiment, a lithographic patterning system comprises an actinic radiation source, where the actinic radiation source is configured to propagate light along an optical axis. In an embodiment, the lithographic patterning system further comprises a mask mount, where the mask mount is configurable to orient a surface of a mask at a first angle with respect to the optical axis. In an embodiment, the lithographic patterning system further comprises a lens module, and a substrate mount, where the substrate mount is configurable to orient a surface of a substrate at a second angle with respect to the optical axis.

公开(公告)号：US20210343673A1

公开(公告)日：2021-11-04

申请号：US17366469

申请日：2021-07-02

Applicant: Intel Corporation

Inventor： Changhua LIU ,  Xiaoying GUO ,  Aleksandar ALEKSOV ,  Steve S. CHO ,  Leonel ARANA ,  Robert MAY ,  Gang DUAN

IPC: H01L23/00

Abstract: A patch structure of an integrated circuit package comprises a core having a first side facing downwards and a second side facing upwards. A first solder resist (SR) layer is formed on the first side of the core, wherein the first SR layer comprises a first layer interconnect (FLI) and has a first set of one or more microbumps thereon to bond to one or more logic die. A second solder resist (SR) layer is formed on the second side of the core, wherein the second SR layer has a second set of one or more microbumps thereon to bond with a substrate. One or more bridge dies includes a respective sets of bumps, wherein the one or more bridge dies is disposed flipped over within the core such that the respective sets of bumps face downward and connect to the first set of one or more microbumps in the FLI.

公开(公告)号：US20190355647A1

公开(公告)日：2019-11-21

申请号：US16527961

申请日：2019-07-31

Applicant: Intel Corporation

Inventor： Aleksandar ALEKSOV ,  Hiroki TANAKA ,  Robert A. MAY ,  Kristof DARMAWIKARTA ,  Changhua LIU ,  Chung Kwang TAN ,  Srinivas PIETAMBARAM ,  Sri Ranga Sai BOYAPATI

IPC: H01L23/485 ,  H01L21/027 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L23/544

Abstract: Techniques that can assist with fabricating a package layer that includes a plurality of dual-damascene zero-misalignment-vias (dual-damascene ZMVs) and a trace between the dual-damascene ZMVs are described. The disclosed techniques allow for the dual-damascene ZMVs and their corresponding trace to be plated simultaneously in a single step or operation. As such, there is little or no misalignment between the dual-damascene ZMVs, the trace, and the metal pads connected to the ZMVs. In this way, one or more of the embodiments described herein can assist with reducing manufacturing costs, reducing development time of fabricating a package layer, and with increasing the I/O density in a semiconductor package.

公开(公告)号：US20240222130A1

公开(公告)日：2024-07-04

申请号：US18091026

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Shaojiang CHEN ,  Jeremy D. ECTON ,  Oladeji FADAYOMI ,  Hsin-Wei WANG ,  Changhua LIU ,  Bin MU ,  Hongxia FENG ,  Brandon C. MARIN ,  Srinivas V. PIETAMBARAM

IPC: H01L21/306 ,  H01L21/321 ,  H01L21/48 ,  H01L21/768

CPC classification number: H01L21/30604 ,  H01L21/3212 ,  H01L21/486 ,  H01L21/7688 ,  H01L21/76898 ,  H01L21/268

Abstract: Embodiments disclosed herein include electronic packages and methods of forming electronic packages. In an embodiment, an electronic package comprises a core, where the core comprises glass. In an embodiment, a through glass via (TGV) is provided through a thickness of the core. In an embodiment, the TGV comprises a top surface that is non-planar and includes a symmetric ridge on the non-planar top surface.