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    FIRST LAYER INTERCONNECT FIRST ON CARRIER APPROACH FOR EMIB PATCH
    2.
    发明申请
    FIRST LAYER INTERCONNECT FIRST ON CARRIER APPROACH FOR EMIB PATCH 有权

    公开(公告)号：US20210343673A1

    公开(公告)日：2021-11-04

    申请号：US17366469

    申请日：2021-07-02

    Applicant: Intel Corporation

    Inventor： Changhua LIU ,  Xiaoying GUO ,  Aleksandar ALEKSOV ,  Steve S. CHO ,  Leonel ARANA ,  Robert MAY ,  Gang DUAN

    IPC: H01L23/00

    Abstract: A patch structure of an integrated circuit package comprises a core having a first side facing downwards and a second side facing upwards. A first solder resist (SR) layer is formed on the first side of the core, wherein the first SR layer comprises a first layer interconnect (FLI) and has a first set of one or more microbumps thereon to bond to one or more logic die. A second solder resist (SR) layer is formed on the second side of the core, wherein the second SR layer has a second set of one or more microbumps thereon to bond with a substrate. One or more bridge dies includes a respective sets of bumps, wherein the one or more bridge dies is disposed flipped over within the core such that the respective sets of bumps face downward and connect to the first set of one or more microbumps in the FLI.

    LITHOGRAPHY PILLAR PROCESS FOR EMBEDDED BRIDGE SCALING
    3.
    发明申请
    LITHOGRAPHY PILLAR PROCESS FOR EMBEDDED BRIDGE SCALING 有权

    公开(公告)号：US20230090350A1

    公开(公告)日：2023-03-23

    申请号：US17478439

    申请日：2021-09-17

    Applicant: Intel Corporation

    Inventor： Kyle MCELHINNY ,  Haobo CHEN ,  Hongxia FENG ,  Xiaoying GUO ,  Leonel ARANA

    IPC: H01L23/538 ,  H01L23/498 ,  H01L21/48 ,  H01L25/065 ,  H01L23/00

    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a package substrate, and a first pad over the package substrate. In an embodiment, a layer is over the package substrate, where the layer is an insulating material. In an embodiment, the electronic package further comprises a via through the layer and in contact with the first pad. In an embodiment a first end of the via has a first width and a second end of the via that is in contact with the first pad has a second width that is larger than the first width. In an embodiment, the electronic package further comprises a second pad over the via.

    EMBEDDED BRIDGE ARCHITECTURE WITH THINNED SURFACE
    4.
    发明申请
    EMBEDDED BRIDGE ARCHITECTURE WITH THINNED SURFACE 有权

    公开(公告)号：US20220310518A1

    公开(公告)日：2022-09-29

    申请号：US17213147

    申请日：2021-03-25

    Applicant: Intel Corporation

    Inventor： Haobo CHEN ,  Xiaoying GUO ,  Hongxia FENG ,  Kristof DARMAWIKARTA ,  Bai NIE ,  Tarek A. IBRAHIM ,  Gang DUAN ,  Jeremy D. ECTON ,  Sheng C. LI ,  Leonel ARANA

    IPC: H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48

    Abstract: Embodiments disclosed herein include a multi-die packages with an embedded bridge and a thinned surface. In an example, a multi-die interconnect structure includes a package substrate having a cavity. A bridge die is in the cavity of the package substrate, the bridge die including silicon. A dielectric material is over the package substrate, over the bridge die, and in the cavity. A plurality of conductive bond pads is on the dielectric material. The multi-die interconnect structure further includes a plurality of conductive pillars, individual ones of the plurality of conductive pillars on a corresponding one of the plurality of conductive bond pads. A solder resist material is on the dielectric material, on exposed portions of the plurality of conductive bond pads, and laterally surrounding the plurality of conductive pillars. The plurality of conductive pillars has a top surface above a top surface of the solder resist material.

    COMPOSITE DRY FILM RESIST FOR PHOTOLITHOGRAPHY
    5.
    发明申请
    COMPOSITE DRY FILM RESIST FOR PHOTOLITHOGRAPHY 有权

    公开(公告)号：US20210318612A1

    公开(公告)日：2021-10-14

    申请号：US17356536

    申请日：2021-06-24

    Applicant: Intel Corporation

    Inventor： Hongxia FENG ,  Changhua LIU ,  Bohan SHAN ,  Dingying XU ,  Leonel ARANA ,  Manuel GADOGBE ,  Matthew TINGEY ,  Julianne TROIANO

    IPC: G03F7/038 ,  G03F7/20 ,  G03F7/32

    Abstract: The present disclosure is directed to a patterning process that includes providing a composite dry film resist on a surface, in which the composite dry film resist includes a base film, a barrier layer and a resist layer, in which the base film is disposed over the barrier layer and the barrier layer is disposed over the resist layer. In another aspect, the patterning process includes removing the base film from the barrier layer and exposing the barrier layer to form an exposure precursor, which has a first area and a second area, further exposing the first area of the exposure precursor to electromagnetic irradiation, which passes through the barrier layer and the resist layer in the exposed first area becomes water-insoluble, and removing the barrier layer and the unexposed second area to form a pattern template.

    TOOLS AND METHODS FOR SURFACE LEVELING
    6.
    发明公开
    TOOLS AND METHODS FOR SURFACE LEVELING 审中-公开

    公开(公告)号：US20240282591A1

    公开(公告)日：2024-08-22

    申请号：US18171683

    申请日：2023-02-21

    Applicant: Intel Corporation

    Inventor： Oladeji FADAYOMI ,  Shaojiang CHEN ,  Jeremy ECTON ,  Matthew TINGEY ,  Srinivas PIETAMBARAM ,  Leonel ARANA

    IPC: H01L21/48 ,  C23F1/02

    CPC classification number: H01L21/486 ,  C23F1/02

    Abstract: The present disclosure is directed to a planarization tool having at least one module with a target holder for supporting a target with a metal layer, at least one of a plurality of etch inhibitor dispensers for discharging an etch inhibitor toward the target, and a plurality of nozzles for discharging a chemical etchant at an angle towards the target to perform selective removal of the metal layer for planarization of the target. In an aspect, the plurality of etch inhibitor dispensers and the plurality of nozzles may be combined as a single unit to discharge the chemical etchant and the etch inhibitor together. In another aspect, the plurality of etch inhibitor dispensers and the plurality of nozzles may be configured in a single module or separate modules.

    FIRST LAYER INTERCONNECT FIRST ON CARRIER APPROACH FOR EMIB PATCH
    8.
    发明申请
    FIRST LAYER INTERCONNECT FIRST ON CARRIER APPROACH FOR EMIB PATCH 有权

    公开(公告)号：US20230027030A1

    公开(公告)日：2023-01-26

    申请号：US17958296

    申请日：2022-09-30

    Applicant: Intel Corporation

    Inventor： Changhua LIU ,  Xiaoying GUO ,  Aleksandar ALEKSOV ,  Steve S. CHO ,  Leonel ARANA ,  Robert MAY ,  Gang DUAN

    IPC: H01L23/00

    Abstract: A patch structure of an integrated circuit package comprises a core having a first side facing downwards and a second side facing upwards. A first solder resist (SR) layer is formed on the first side of the core, wherein the first SR layer comprises a first layer interconnect (FLI) and has a first set of one or more microbumps thereon to bond to one or more logic die. A second solder resist (SR) layer is formed on the second side of the core, wherein the second SR layer has a second set of one or more microbumps thereon to bond with a substrate. One or more bridge dies includes a respective sets of bumps, wherein the one or more bridge dies is disposed flipped over within the core such that the respective sets of bumps face downward and connect to the first set of one or more microbumps in the FLI.

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