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公开(公告)号：US20200242003A1
公开(公告)日：2020-07-30
申请号：US16699871
申请日：2019-12-02
申请人： Intel Corporation
发明人： Matthew C. Merten , Beeman C. Strong , Michael W. Chynoweth , Grant G. Zhou , Andreas Kleen , Kimberly C. Weier , Angela D. Schmid , Stanislav Bratanov , Seth Abraham , Jason W. Brandt , Ahmad Yasin
摘要： A processor is to execute and retire instructions for a virtual machine. A reload register is coupled to the core is to store a reload value. A performance monitoring counter (PMC) register is coupled to the reload register and an event-based sampler operatively is coupled to the reload register and the PMC register. The event-based sampler includes circuitry to load the reload value into the PMC register and increment the PMC register after detecting each occurrence of an event of a certain type as a result of execution of the instructions. Upon detecting an occurrence of the event after the PMC register reaches a predetermined trigger value, the event-based sampler is to execute microcode to generate field data for elements within a sampling record, wherein the field data relates to a current processor state of execution, and reload the reload value from the reload register into the PMC register.
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公开(公告)号：US10445204B2
公开(公告)日：2019-10-15
申请号：US14865715
申请日：2015-09-25
申请人： Intel Corporation
摘要： A processor includes a processor trace logical unit to produce branch execution records from execution of instructions. The processor further includes logic to determine that a condition has occurred on the processor during execution of the instructions. The condition is to include an asynchronous event or a return from a software handler for an asynchronous event. The processor further includes logic to determine whether event tracing is enabled for the processor. The processor also includes logic to generate a control flow event (CFE) packet. The CFE packet is to indicate a type of the condition. The processor further includes logic to generate an indicator of an instruction address that generated the condition.
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公开(公告)号：US20190188115A1
公开(公告)日：2019-06-20
申请号：US16284581
申请日：2019-02-25
申请人： Intel Corporation
IPC分类号： G06F11/36 , G06F9/30 , G06F9/38 , G06F12/0875
CPC分类号： G06F11/3648 , G06F9/3004 , G06F9/30145 , G06F9/3017 , G06F9/3877 , G06F11/3476 , G06F11/3636 , G06F12/0875 , G06F2212/452
摘要： There is disclosed in an example a processor, having: a front end including circuitry to decode instructions from an instruction stream; a data cache unit including circuitry to cache data for the processor; and a core triggering block (CTB) to provide integration between two or more different debug capabilities.
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公开(公告)号：US20230092268A1
公开(公告)日：2023-03-23
申请号：US17992407
申请日：2022-11-22
申请人： Intel Corporation
发明人： Michael W. Chynoweth , Jonathan D. Combs , Joseph K. Olivas , Beeman C. Strong , Rajshree A. Chabukswar , Ahmad Yasin , Jason W. Brandt , Ofer Levy , John M. Esper , Andreas Kleen , Christopher M. Chrulski
IPC分类号： G06F9/30
摘要： A processor includes a counter to store a cycle count that tracks a number of cycles between retirement of a first branch instruction and retirement of a second branch instruction during execution of a set of instructions. The processor further includes a stack of registers coupled to the counter, wherein the stack of registers is to store branch type information including: a first value of the counter when the first branch instruction is retired; a second value of the counter when the second branch instruction is retired; a first type information value indicating a type of the first branch instruction; and a second type information value indicating a type of the second branch instruction.
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公开(公告)号：US20180217839A1
公开(公告)日：2018-08-02
申请号：US15423143
申请日：2017-02-02
申请人： INTEL CORPORATION
发明人： Michael W. Chynoweth , Jonathan D. Combs , Joseph K. Olivas , Beeman C. Strong , Rajshree A. Chabukswar , Ahmad Yasin , Jason W. Brandt , Ofer Levy , John M. Esper , Andreas Kleen , Christopher M. Chrulski
CPC分类号： G06F9/3005
摘要： An example processor that includes a decoder, an execution circuit, a counter, and a last branch recorder (LBR) register. The decoder may decode a branch instruction for a program. The execution circuit may be coupled to the decoder, where the execution circuit may execute the branch instruction. The counter may be coupled to the execution circuit, where the counter may store a cycle count. The LBR register coupled to the execution circuit, where the LBR register may include a counter field to store a first value of the counter when the branch instruction is executed and a type field to store type information indicating a type of the branch instruction.
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公开(公告)号：US09612938B2
公开(公告)日：2017-04-04
申请号：US13895595
申请日：2013-05-16
申请人： Intel Corporation
发明人： Frank Binns , Matthew C. Merten , Mayank Bomb , Beeman C. Strong , Peter Lachner , Jason W. Brandt , Itamar Kazachinsky , Ofer Levy , Md A. Rahman
CPC分类号： G06F11/3636 , G06F11/3024 , G06F11/3055 , G06F11/3476 , G06F11/348 , G06F2201/865
摘要： In accordance with embodiments disclosed herein, there is provided systems and methods for providing status of a processing device with a periodic synchronization point in an instruction tracing system. For example, the method may include generating a boundary packet based on a unique byte pattern in a packet log. The boundary packet provides a starting point for packet decode. The method may also include generating a plurality of state packets based on status information of the processor. The plurality of state packets follows the boundary packet when outputted into the packet log.
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公开(公告)号：US20160378636A1
公开(公告)日：2016-12-29
申请号：US14751759
申请日：2015-06-26
申请人： Intel Corporation
发明人： Beeman C. Strong , Jason W. Brandt , Peter Lachner , Andreas Kleen , James B. Crossland , Toby Opferman
CPC分类号： G06F11/3466 , G06F11/3024 , G06F2201/865
摘要： In an embodiment, a processor includes a core that is to include fetch logic to fetch instructions that include first instructions and a second instruction. The core also includes execution logic to execute the instructions. The execution logic is to retrieve an operand value that is one of an immediate value, a register value, and a memory value stored in a memory location, responsive to execution of the second instruction. The core also includes logic to output a packet that includes a representation of the operand value responsive to execution of the second instruction. The core also includes processor trace (PT) logic to generate a processor trace that includes a plurality of PT packets, where each PT packet correspond to an outcome of execution of a respective first instruction. The processor trace logic is further to include the packet within the processor trace. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，处理器包括一个核心，其核心是包括提取逻辑，以提取包括第一指令和第二指令的指令。 核心还包括执行指令的执行逻辑。 执行逻辑是响应于第二指令的执行，检索作为立即值，寄存器值和存储在存储单元中的存储器值之一的操作数值。 核心还包括输出包括响应于执行第二指令的操作数值的表示的数据包的逻辑。 核心还包括处理器跟踪（PT）逻辑以产生包括多个PT分组的处理器跟踪，其中每个PT分组对应于相应的第一指令的执行结果。 处理器跟踪逻辑进一步将数据包包含在处理器跟踪内。 描述和要求保护其他实施例。
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公开(公告)号：US11055203B2
公开(公告)日：2021-07-06
申请号：US16699871
申请日：2019-12-02
申请人： Intel Corporation
发明人： Matthew C. Merten , Beeman C. Strong , Michael W. Chynoweth , Grant G. Zhou , Andreas Kleen , Kimberly C. Weier , Angela D. Schmid , Stanislav Bratanov , Seth Abraham , Jason W. Brandt , Ahmad Yasin
摘要： A processor is to execute and retire instructions for a virtual machine. A reload register is coupled to the core is to store a reload value. A performance monitoring counter (PMC) register is coupled to the reload register and an event-based sampler operatively is coupled to the reload register and the PMC register. The event-based sampler includes circuitry to load the reload value into the PMC register and increment the PMC register after detecting each occurrence of an event of a certain type as a result of execution of the instructions. Upon detecting an occurrence of the event after the PMC register reaches a predetermined trigger value, the event-based sampler is to execute microcode to generate field data for elements within a sampling record, wherein the field data relates to a current processor state of execution, and reload the reload value from the reload register into the PMC register.
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9.发明申请公开(公告)号：US20170286111A1
公开(公告)日：2017-10-05
申请号：US15089179
申请日：2016-04-01
申请人： Intel Corporation
CPC分类号： G06F12/0875 , G06F11/3034 , G06F11/3466 , G06F12/0842 , G06F12/0888 , G06F2201/865 , G06F2212/452
摘要： A processor includes a front end including circuitry to receive an instruction to monitor execution of a thread, a decoder including circuitry to decode the instruction, a scheduler including circuitry to schedule the instruction, a retirement unit including circuitry to retire the instruction, and a core. The core includes circuitry to, based on execution of the instruction, monitor execution of the thread, identify an attempted read of an address during execution of the thread, determine whether a value at the address was previously read during monitoring of the execution of the thread, log the attempted read based on a determination that the value at the address was not previously read during monitoring of the execution of the thread, and omit logging of the attempted read based on a determination that the value at the address was previously read during monitoring of the execution of the thread.
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公开(公告)号：US09632907B2
公开(公告)日：2017-04-25
申请号：US14566374
申请日：2014-12-10
申请人： Intel Corporation
CPC分类号： G06F11/3466 , G06F9/30 , G06F11/3636
摘要： A processing device implementing tracking of deferred data packets in a debug trace architecture is disclosed. The processing device is to determine an order number corresponding to an order in which an instruction was executed relative to other executed instructions that correspond to an instruction type within a sequence of executed instructions, identify a first data packet corresponding to a first packet type and sequentially ordered, according to the order number, with respect to data packets of the first packet type within a data trace log, identify a second data packet corresponding to a second packet type and sequentially ordered, according to the order number, with respect to data packets of the second packet type within the data trace log, and map the identified first and second data packets to the instruction, wherein at least one of the first or second data packets was generated post-retirement of the instruction.
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