公开(公告)号：US12020031B2

公开(公告)日：2024-06-25

申请号：US17334901

申请日：2021-05-31

申请人： Intel Corporation

发明人： Michael Mishaeli ,  Jason W. Brandt ,  Gilbert Neiger ,  Asit K. Mallick ,  Rajesh M. Sankaran ,  Raghunandan Makaram ,  Benjamin C. Chaffin ,  James B. Crossland ,  H. Peter Anvin

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F13/40

CPC分类号： G06F9/3009 ,  G06F9/3004 ,  G06F9/30076 ,  G06F9/3851 ,  G06F9/485 ,  G06F13/4068

摘要： A processor of an aspect includes a decode unit to decode a user-level suspend thread instruction that is to indicate a first alternate state. The processor also includes an execution unit coupled with the decode unit. The execution unit is to perform the instruction at a user privilege level. The execution unit in response to the instruction, is to: (a) suspend execution of a user-level thread, from which the instruction is to have been received; (b) transition a logical processor, on which the user-level thread was to have been running, to the indicated first alternate state; and (c) resume the execution of the user-level thread, when the logical processor is in the indicated first alternate state, with a latency that is to be less than half a latency that execution of a thread can be resumed when the logical processor is in a halt processor power state.

公开(公告)号：US11966742B2

公开(公告)日：2024-04-23

申请号：US18311810

申请日：2023-05-03

申请人： Intel Corporation

发明人： Eliezer Weissmann ,  Mark Charney ,  Michael Mishaeli ,  Robert Valentine ,  Itai Ravid ,  Jason W. Brandt ,  Gilbert Neiger ,  Baruch Chaikin ,  Efraim Rotem

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3851 ,  G06F9/30043 ,  G06F9/30076 ,  G06F9/30101 ,  G06F9/3836 ,  G06F9/3842

摘要： Systems, methods, and apparatuses relating to instructions to reset software thread runtime property histories in a hardware processor are described. In one embodiment, a hardware processor includes a hardware guide scheduler comprising a plurality of software thread runtime property histories; a decoder to decode a single instruction into a decoded single instruction, the single instruction having a field that identifies a model-specific register; and an execution circuit to execute the decoded single instruction to check that an enable bit of the model-specific register is set, and when the enable bit is set, to reset the plurality of software thread runtime property histories of the hardware guide scheduler.

公开(公告)号：US11650818B2

公开(公告)日：2023-05-16

申请号：US17404890

申请日：2021-08-17

申请人： Intel Corporation

发明人： Vedvyas Shanbhogue ,  Jason W. Brandt ,  Ravi L. Sahita ,  Xiaoning Li

IPC分类号： G06F21/54 ,  G06F21/00 ,  G06F9/30 ,  G06F9/38 ,  G06F21/55

CPC分类号： G06F9/3005 ,  G06F9/30054 ,  G06F9/30145 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/3865 ,  G06F9/3867 ,  G06F21/554

摘要： A processor includes an execution unit and a processing logic operatively coupled to the execution unit, the processing logic to: enter a first execution state and transition to a second execution state responsive to executing a control transfer instruction. Responsive to executing a target instruction of the control transfer instruction, the processing logic further transitions to the first execution state responsive to the target instruction being a control transfer termination instruction of a mode identical to a mode of the processing logic following the execution of the control transfer instruction; and raises an execution exception responsive to the target instruction being a control transfer termination instruction of a mode different than the mode of the processing logic following the execution of the control transfer instruction.

公开(公告)号：US20230092268A1

公开(公告)日：2023-03-23

申请号：US17992407

申请日：2022-11-22

申请人： Intel Corporation

发明人： Michael W. Chynoweth ,  Jonathan D. Combs ,  Joseph K. Olivas ,  Beeman C. Strong ,  Rajshree A. Chabukswar ,  Ahmad Yasin ,  Jason W. Brandt ,  Ofer Levy ,  John M. Esper ,  Andreas Kleen ,  Christopher M. Chrulski

IPC分类号： G06F9/30

摘要： A processor includes a counter to store a cycle count that tracks a number of cycles between retirement of a first branch instruction and retirement of a second branch instruction during execution of a set of instructions. The processor further includes a stack of registers coupled to the counter, wherein the stack of registers is to store branch type information including: a first value of the counter when the first branch instruction is retired; a second value of the counter when the second branch instruction is retired; a first type information value indicating a type of the first branch instruction; and a second type information value indicating a type of the second branch instruction.

公开(公告)号：US20220413859A1

公开(公告)日：2022-12-29

申请号：US17358082

申请日：2021-06-25

申请人： Intel Corporation

发明人： Kameswar Subramaniam ,  Jason W. Brandt ,  H. Peter Anvin ,  Christopher M. Russell ,  Gilbert Neiger

IPC分类号： G06F9/30 ,  G06F9/455 ,  G06F9/48

摘要： In one embodiment, a processor includes: a front end circuit to fetch and decode a read list instruction, the read list instruction to cause storage to a memory of a software-provided list of processor state information; and an execution circuit coupled to the front end circuit. The execution circuit, in response to the decoded read list instruction, is to read the processor state information stored in the processor and store each datum of the processor state information into an entry of a data table in the memory. Other embodiments are described and claimed.

公开(公告)号：US20220335126A1

公开(公告)日：2022-10-20

申请号：US17590470

申请日：2022-02-01

申请人： Intel Corporation

发明人： Robert S. Chappell ,  Jared W. Stark, IV ,  Joseph Nuzman ,  Stephen Robinson ,  Jason W. Brandt

IPC分类号： G06F21/55 ,  G06F21/62 ,  G06F9/48 ,  G06F12/0802 ,  G06F9/30

摘要： Systems, methods, and apparatuses relating to microarchitectural mechanisms for the prevention of side-channel attacks are disclosed herein. In one embodiment, a processor includes a core having a plurality of physical contexts to execute a plurality of threads, a plurality of structures shared by the plurality of threads, a context mapping structure to map context signatures to respective physical contexts of the plurality of physical contexts, each physical context to identify and differentiate state of the plurality of structures, and a context manager circuit to, when one or more of a plurality of fields that comprise a context signature is changed, search the context mapping structure for a match to another context signature, and when the match is found, a physical context associated with the match is set as an active physical context for the core.

公开(公告)号：US11416624B2

公开(公告)日：2022-08-16

申请号：US16722707

申请日：2019-12-20

申请人： Intel Corporation

发明人： David M. Durham ,  Michael LeMay ,  Ramya Jayaram Masti ,  Gilbert Neiger ,  Jason W. Brandt

IPC分类号： G06F21/60 ,  G06F9/30 ,  G06F21/72 ,  G06F21/79 ,  G06F21/12 ,  H04L9/08 ,  G06F12/14 ,  H04L9/14 ,  G06F21/62 ,  G06F12/0897 ,  G06F9/48 ,  H04L9/06 ,  G06F12/06 ,  G06F12/0875 ,  G06F12/0811 ,  G06F9/32 ,  G06F9/50 ,  G06F12/02 ,  G06F9/455

摘要： Technologies disclosed herein provide cryptographic computing with cryptographically encoded pointers in multi-tenant environments. An example method comprises executing, by a trusted runtime, first instructions to generate a first address key for a private memory region in the memory and generate a first cryptographically encoded pointer to the private memory region in the memory. Generating the first cryptographically encoded pointer includes storing first context information associated with the private memory region in first bits of the first cryptographically encoded pointer and performing a cryptographic algorithm on a slice of a first linear address of the private memory region based, at least in part, on the first address key and a first tweak, the first tweak including the first context information. The method further includes permitting a first tenant in the multi-tenant environment to access the first address key and the first cryptographically encoded pointer to the private memory region.

公开(公告)号：US20220237123A1

公开(公告)日：2022-07-28

申请号：US17712632

申请日：2022-04-04

申请人： Intel Corporation

发明人： Jason W. Brandt ,  Robert S. Chappell ,  Jesus Corbal ,  Edward T. Grochowski ,  Stephen H. Gunther ,  Buford M. Guy ,  Thomas R. Huff ,  Christopher J. Hughes ,  Elmoustapha Ould-Ahmed-Vall ,  Ronak Singhal ,  Seyed Yahya Sotoudeh ,  Bret L. Toll ,  Lihu Rappoport ,  David B. Papworth ,  James D. Allen

IPC分类号： G06F12/0831 ,  G06F12/1027 ,  G06F12/1009 ,  G06F9/30

摘要： Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a cache line sized write of zeros. The coherent cache is to receive the write command, to determine whether there is a hit in the coherent cache and whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros, and to issue the write command toward the interconnect. The interconnect is to, responsive to receipt of the write command, issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit.

公开(公告)号：US20220207138A1

公开(公告)日：2022-06-30

申请号：US17134350

申请日：2020-12-26

申请人： Intel Corporation

发明人： Carlos Rozas ,  Fangfei Liu ,  Xiang Zou ,  Francis McKeen ,  Jason W. Brandt ,  Joseph Nuzman ,  Alaa Alameldeen ,  Abhishek Basak ,  Scott Constable ,  Thomas Unterluggauer ,  Asit Mallick ,  Matthew Fernandez

IPC分类号： G06F21/55 ,  G06F21/54 ,  G06F9/30 ,  G06F9/38

摘要： Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes a decode circuitry and store circuitry coupled to the decode circuitry. The decode circuitry is to decode a store hardening instruction to mitigate vulnerability to a speculative execution attack. The store circuitry is to be hardened in response to the store hardening instruction.

公开(公告)号：US20220019432A1

公开(公告)日：2022-01-20

申请号：US17404890

申请日：2021-08-17

申请人： Intel Corporation

发明人： Vedvyas Shanbhogue ,  Jason W. Brandt ,  Ravi L. Sahita ,  Xiaoning Li

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F21/55

摘要： A processor includes an execution unit and a processing logic operatively coupled to the execution unit, the processing logic to: enter a first execution state and transition to a second execution state responsive to executing a control transfer instruction. Responsive to executing a target instruction of the control transfer instruction, the processing logic further transitions to the first execution state responsive to the target instruction being a control transfer termination instruction of a mode identical to a mode of the processing logic following the execution of the control transfer instruction; and raises an execution exception responsive to the target instruction being a control transfer termination instruction of a mode different than the mode of the processing logic following the execution of the control transfer instruction.