公开(公告)号：US20230092268A1

公开(公告)日：2023-03-23

申请号：US17992407

申请日：2022-11-22

申请人： Intel Corporation

发明人： Michael W. Chynoweth ,  Jonathan D. Combs ,  Joseph K. Olivas ,  Beeman C. Strong ,  Rajshree A. Chabukswar ,  Ahmad Yasin ,  Jason W. Brandt ,  Ofer Levy ,  John M. Esper ,  Andreas Kleen ,  Christopher M. Chrulski

IPC分类号： G06F9/30

摘要： A processor includes a counter to store a cycle count that tracks a number of cycles between retirement of a first branch instruction and retirement of a second branch instruction during execution of a set of instructions. The processor further includes a stack of registers coupled to the counter, wherein the stack of registers is to store branch type information including: a first value of the counter when the first branch instruction is retired; a second value of the counter when the second branch instruction is retired; a first type information value indicating a type of the first branch instruction; and a second type information value indicating a type of the second branch instruction.

公开(公告)号：US20190286559A1

公开(公告)日：2019-09-19

申请号：US16433671

申请日：2019-06-06

申请人： Intel Corporation

发明人： Avinash Sodani ,  Robert J. Kyanko ,  Richard J. Greco ,  Andreas Kleen ,  Milind B. Girkar ,  Christopher M. Cantalupo

IPC分类号： G06F12/06 ,  G06F12/02

摘要： In one embodiment, a processor comprises: at least one core formed on a die to execute instructions; a first memory controller to interface with an in-package memory; a second memory controller to interface with a platform memory to couple to the processor; and the in-package memory located within a package of the processor, where the in-package memory is to be identified as a more distant memory with respect to the at least one core than the platform memory. Other embodiments are described and claimed.

公开(公告)号：US20180217839A1

公开(公告)日：2018-08-02

申请号：US15423143

申请日：2017-02-02

申请人： INTEL CORPORATION

发明人： Michael W. Chynoweth ,  Jonathan D. Combs ,  Joseph K. Olivas ,  Beeman C. Strong ,  Rajshree A. Chabukswar ,  Ahmad Yasin ,  Jason W. Brandt ,  Ofer Levy ,  John M. Esper ,  Andreas Kleen ,  Christopher M. Chrulski

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/3005

摘要： An example processor that includes a decoder, an execution circuit, a counter, and a last branch recorder (LBR) register. The decoder may decode a branch instruction for a program. The execution circuit may be coupled to the decoder, where the execution circuit may execute the branch instruction. The counter may be coupled to the execution circuit, where the counter may store a cycle count. The LBR register coupled to the execution circuit, where the LBR register may include a counter field to store a first value of the counter when the branch instruction is executed and a type field to store type information indicating a type of the branch instruction.

公开(公告)号：US20170177463A1

公开(公告)日：2017-06-22

申请号：US14977071

申请日：2015-12-21

申请人： Intel Corporation

发明人： Andreas Kleen

IPC分类号： G06F11/36

CPC分类号： G06F11/3644 ,  G06F11/34 ,  G06F11/3624 ,  G06F11/366

摘要： A program control flow trace is obtained from a processor trace module, which may be hardware based, and is used, in combination with debug information and information from dissassembly of basic blocks, to identify candidate store instruction(s) which produced a memory corruption. The candidate store instruction(s) and links to a software program may be used to further debug the memory corruption and/or to instrument the software program to identify basic block(s) which produced the memory corruption in future executions of the compiled software program and/or to track debugging of the software program.

公开(公告)号：US20160378636A1

公开(公告)日：2016-12-29

申请号：US14751759

申请日：2015-06-26

申请人： Intel Corporation

发明人： Beeman C. Strong ,  Jason W. Brandt ,  Peter Lachner ,  Andreas Kleen ,  James B. Crossland ,  Toby Opferman

IPC分类号： G06F11/34 ,  G06F11/30

CPC分类号： G06F11/3466 ,  G06F11/3024 ,  G06F2201/865

摘要： In an embodiment, a processor includes a core that is to include fetch logic to fetch instructions that include first instructions and a second instruction. The core also includes execution logic to execute the instructions. The execution logic is to retrieve an operand value that is one of an immediate value, a register value, and a memory value stored in a memory location, responsive to execution of the second instruction. The core also includes logic to output a packet that includes a representation of the operand value responsive to execution of the second instruction. The core also includes processor trace (PT) logic to generate a processor trace that includes a plurality of PT packets, where each PT packet correspond to an outcome of execution of a respective first instruction. The processor trace logic is further to include the packet within the processor trace. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，处理器包括一个核心，其核心是包括提取逻辑，以提取包括第一指令和第二指令的指令。 核心还包括执行指令的执行逻辑。 执行逻辑是响应于第二指令的执行，检索作为立即值，寄存器值和存储在存储单元中的存储器值之一的操作数值。 核心还包括输出包括响应于执行第二指令的操作数值的表示的数据包的逻辑。 核心还包括处理器跟踪（PT）逻辑以产生包括多个PT分组的处理器跟踪，其中每个PT分组对应于相应的第一指令的执行结果。 处理器跟踪逻辑进一步将数据包包含在处理器跟踪内。 描述和要求保护其他实施例。

公开(公告)号：US20210240609A1

公开(公告)日：2021-08-05

申请号：US17119679

申请日：2020-12-11

申请人： Intel Corporation

发明人： Omid Azizi ,  Amin Firoozshahian ,  Andreas Kleen ,  Mahesh Madhav ,  Mahesh Maddury ,  Chandan Egbert ,  Eric Gouldey

IPC分类号： G06F12/02 ,  G06F9/50 ,  G06F3/06

摘要： Various systems and methods for computer memory overcommitment management are described herein. A system for computer memory management includes a memory device to store data and a mapping table; and a memory overcommitment circuitry to: receive a signal to move data in a first block from a memory reduction area in the memory device to a non-memory reduction area in the memory device, the memory reduction area to store data using a memory reduction technique, and the non-memory reduction area to store data without any memory reduction techniques; allocate a second block in the non-memory reduction area; copy the data in the first block to the second block; and update the mapping table to revise a pointer to point to the second block, the mapping table used to store pointers to memory device in the memory reduction area and the non-memory reduction area.

公开(公告)号：US11055203B2

公开(公告)日：2021-07-06

申请号：US16699871

申请日：2019-12-02

申请人： Intel Corporation

发明人： Matthew C. Merten ,  Beeman C. Strong ,  Michael W. Chynoweth ,  Grant G. Zhou ,  Andreas Kleen ,  Kimberly C. Weier ,  Angela D. Schmid ,  Stanislav Bratanov ,  Seth Abraham ,  Jason W. Brandt ,  Ahmad Yasin

IPC分类号： G06F11/36 ,  G06F9/455 ,  H04L12/24 ,  H04L12/26

摘要： A processor is to execute and retire instructions for a virtual machine. A reload register is coupled to the core is to store a reload value. A performance monitoring counter (PMC) register is coupled to the reload register and an event-based sampler operatively is coupled to the reload register and the PMC register. The event-based sampler includes circuitry to load the reload value into the PMC register and increment the PMC register after detecting each occurrence of an event of a certain type as a result of execution of the instructions. Upon detecting an occurrence of the event after the PMC register reaches a predetermined trigger value, the event-based sampler is to execute microcode to generate field data for elements within a sampling record, wherein the field data relates to a current processor state of execution, and reload the reload value from the reload register into the PMC register.

公开(公告)号：US20190196988A1

公开(公告)日：2019-06-27

申请号：US15855798

申请日：2017-12-27

申请人： Intel Corporation

发明人： Ishwar Agarwal ,  Omid Azizi ,  Chandan Egbert ,  Amin Firoozshahian ,  David Christopher Hansen ,  Andreas Kleen ,  Mahesh Maddury ,  Mahesh Madhav ,  Ashok Raj ,  Alexandre Solomatnikov ,  Stephen Van Doren

IPC分类号： G06F13/16 ,  G06F3/06

CPC分类号： G06F13/1668 ,  G06F3/0604 ,  G06F3/0653 ,  G06F3/0673 ,  G06F2213/24

摘要： Various systems and methods for computer memory management are described herein. A system includes a memory controller to: monitor utilization of a memory device, the memory device used with a memory compression technique; determine that the utilization of the memory device violates a threshold; and initiate a system interrupt to provoke a response, responsive to the utilization of the memory device violating the threshold.

公开(公告)号：US20170357580A1

公开(公告)日：2017-12-14

申请号：US15628811

申请日：2017-06-21

申请人： Intel Corporation

发明人： Avinash Sodani ,  Robert J. Kyanko ,  Richard J. Greco ,  Andreas Kleen ,  Milind B. Girkar ,  Christopher M. Cantalupo

IPC分类号： G06F12/06 ,  G06F12/02

CPC分类号： G06F12/0646 ,  G06F12/023 ,  G06F2212/283

摘要： In one embodiment, a processor comprises: at least one core formed on a die to execute instructions; a first memory controller to interface with an in-package memory; a second memory controller to interface with a platform memory to couple to the processor; and the in-package memory located within a package of the processor, where the in-package memory is to be identified as a more distant memory with respect to the at least one core than the platform memory. Other embodiments are described and claimed.

公开(公告)号：US09715416B2

公开(公告)日：2017-07-25

申请号：US14729914

申请日：2015-06-03

申请人： Intel Corporation

发明人： Shou C. Chen ,  Andreas Kleen

IPC分类号： G06F9/46 ,  G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F9/52 ,  G06F9/50 ,  G06F9/48

CPC分类号： G06F9/528 ,  G06F9/467 ,  G06F9/48 ,  G06F9/4881 ,  G06F9/50 ,  G06F9/5005 ,  G06F9/5011 ,  G06F9/5016 ,  G06F9/5022 ,  G06F9/52 ,  G06F9/526

摘要： Adaptive queued locking for control of speculative execution is disclosed. An example apparatus includes a lock to: enforce a first quota to control a number of threads allowed to concurrently speculatively execute after being placed in a queue; and in response to the first quota not having been reached, enable a first thread from the queue to speculatively execute; and an adjuster to change a first value of the first quota based on a result of the speculative execution of the first thread.