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    TECHNOLOGIES FOR TRUSTED I/O WITH A CHANNEL IDENTIFIER FILTER AND PROCESSOR-BASED CRYPTOGRAPHIC ENGINE
    3.
    发明申请
    TECHNOLOGIES FOR TRUSTED I/O WITH A CHANNEL IDENTIFIER FILTER AND PROCESSOR-BASED CRYPTOGRAPHIC ENGINE 审中-公开

    公开(公告)号：US20170364707A1

    公开(公告)日：2017-12-21

    申请号：US15628008

    申请日：2017-06-20

    Applicant: Intel Corporation

    Inventor： Reshma Lal ,  Gideon Gerzon ,  Baruch Chaikin ,  Siddhartha Chhabra ,  Pradeep M. Pappachan ,  Bin Xing

    IPC: G06F21/62 ,  G06F21/57 ,  G06F21/60 ,  G06F13/20 ,  G06F21/51

    Abstract: Technologies for trusted I/O include a computing device having a processor, a channel identifier filter, and an I/O controller. The I/O controller may generate an I/O transaction that includes a channel identifier and a memory address. The channel identifier filter verifies that the memory address of the I/O transaction is within a processor reserved memory region associated with the channel identifier. The processor reserved memory region is not accessible to software executed by the computing device. The processor encrypts I/O data at the memory address in response to invocation of a processor feature and copies the encrypted data to a memory buffer outside of the processor reserved memory region. The processor may securely clean the processor reserved memory region before encrypting and copying the data. The processor may wrap and unwrap programming information for the channel identifier filter. Other embodiments are described and claimed.

    Using Trusted Execution Environments for Security of Code and Data
    4.
    发明申请
    Using Trusted Execution Environments for Security of Code and Data 有权
    使用可信执行环境来实现代码和数据的安全

    公开(公告)号：US20160171248A1

    公开(公告)日：2016-06-16

    申请号：US14572060

    申请日：2014-12-16

    Applicant: Intel Corporation

    Inventor： Nadav Nesher ,  Alex Berenzon ,  Baruch Chaikin

    IPC: G06F21/71 ,  G06F21/60

    CPC classification number: G06F21/53 ,  G06F21/57 ,  G06F21/71 ,  H04L2209/127

    Abstract: An embodiment includes a processor coupled to memory to perform operations comprising: creating a first trusted execution environment (TXE), in protected non-privileged user address space of the memory, which makes a first measurement for at least one of first data and first executable code and which encrypts the first measurement with a persistent first hardware based encryption key while the first measurement is within the first TXE; creating a second TXE, in the non-privileged user address space, which makes a second measurement for at least one of second data and second executable code; creating a third TXE in the non-privileged user address space; creating a first secure communication channel between the first and third TXEs and a second secure communication channel between the second and third TXEs; and communicating the first measurement between the first and third TXEs via the first secure communication channel. Other embodiments are described herein.

    Abstract translation: 实施例包括耦合到存储器以执行操作的处理器，其包括：在存储器的受保护非特权用户地址空间中创建第一可信执行环境（TXE），其对第一数据和第一可执行文件中的至少一个进行第一测量 代码，并且其在第一测量在第一TXE内时利用持久的基于硬件的第一硬件加密密钥对第一测量进行加密; 在非特权用户地址空间中创建第二TXE，其为第二数据和第二可执行代码中的至少一个进行第二测量; 在非特权用户地址空间中创建第三个TXE; 在第一和第三TXE之间创建第一安全通信信道，以及第二和第三TXE之间的第二安全通信信道; 以及经由所述第一安全通信信道在所述第一和第三TXE之间传送所述第一测量。 本文描述了其它实施例。

    Device, system and method to efficiently update a secure arbitration mode module
    10.
    发明授权
    Device, system and method to efficiently update a secure arbitration mode module 有权

    公开(公告)号：US12153665B2

    公开(公告)日：2024-11-26

    申请号：US17133455

    申请日：2020-12-23

    Applicant: Intel Corporation

    Inventor： Vedvyas Shanbhogue ,  Baruch Chaikin

    IPC: G06F21/53 ,  G06F9/30 ,  G06F9/38 ,  G06F9/445 ,  G06F9/455 ,  G06F9/52

    Abstract: Techniques and mechanisms to efficiently provide features of a secure authentication mode (SEAM) by a processor. In an embodiment, cores of the processor support an instruction set which comprises instructions to invoke the SEAM. One such core installs an authenticated code module (ACM), which is executed to load a persistent SEAM loader module (P-SEAMLDR) in a reserved region of a system memory. In turn, the P-SEAMLDR loads into the reserved region a SEAM module which facilitates trust domain extension (TDX) protections for a given trusted domain. In another embodiment, the instruction set supports a SEAM call instruction with which either of the P-SEAMLDR or the SEAM module is accessed in the reserved region.

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