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    Processor with memory race recorder to record thread interleavings in multi-threaded software
    2.
    发明授权
    Processor with memory race recorder to record thread interleavings in multi-threaded software 有权
    具有内存种族记录器的处理器可在多线程软件中记录线程交错

    公开(公告)号：US09128781B2

    公开(公告)日：2015-09-08

    申请号：US13729718

    申请日：2012-12-28

    Applicant: Intel Corporation

    Inventor： Tim Kranich ,  Gilles A. Pokam ,  Justin E. Gottschlich ,  Klaus Danne ,  Rolf Kassa ,  Shiliang Hu ,  Cristiano L. Pereira

    IPC: G06F9/52 ,  G06F11/36

    CPC classification number: G06F9/526 ,  G06F11/3404 ,  G06F11/3409 ,  G06F11/3471 ,  G06F11/36 ,  G06F11/3636

    Abstract: A processor includes a first core to execute a first software thread, a second core to execute a second software thread, and shared memory access monitoring and recording logic. The logic includes memory access monitor logic to monitor accesses to memory by the first thread, record memory addresses of the monitored accesses, and detect data races involving the recorded memory addresses with other threads. The logic includes chunk generation logic is to generate chunks to represent committed execution of the first thread. Each of the chunks is to include a number of instructions of the first thread executed and committed and a time stamp. The chunk generation logic is to stop generation of a current chunk in response to detection of a data race by the memory access monitor logic. A chunk buffer is to temporarily store chunks until the chunks are transferred out of the processor.

    Abstract translation: 处理器包括执行第一软件线程的第一核，执行第二软件线程的第二核和共享存储器存取监视和记录逻辑。 该逻辑包括存储器访问监视器逻辑，以监视第一线程对存储器的访问，记录被监视的访问的存储器地址，以及检测与其他线程相关的记录存储器地址的数据比赛。 逻辑包括块生成逻辑是生成块来表示第一个线程的提交执行。 每个块都包括执行和提交的第一个线程的一些指令和一个时间戳。 块生成逻辑是通过存储器访问监视器逻辑来检测数据竞赛来停止生成当前块。 块缓冲区是临时存储块，直到块被从处理器传出。

    Techniques for detecting race conditions
    3.
    发明授权
    Techniques for detecting race conditions 有权

    公开(公告)号：US10120781B2

    公开(公告)日：2018-11-06

    申请号：US15026515

    申请日：2013-12-12

    Applicant: INTEL CORPORATION

    Inventor： Shiliang Hu ,  Gilles A. Pokam ,  Cristiano L. Pereira ,  Justin E. Gottschlich

    IPC: G06F9/44 ,  G06F9/45 ,  G06F11/36 ,  G06F9/52 ,  G06F11/30 ,  G06F11/34

    Abstract: Various embodiments are generally directed to detecting race conditions arising from uncoordinated data accesses by different portions of an application routine by detecting occurrences of a selected cache event associated with such accesses. An apparatus includes a processor component; a trigger component for execution by the processor component to configure a monitoring unit of the processor component to detect a cache event associated with a race condition between accesses to a piece of data and to capture an indication of a state of the processor component to generate monitoring data in response to an occurrence of the cache event; and a counter component for execution by the processor component to configure a counter of the monitoring unit to enable capture of the indication of the state of the processor component at a frequency less than every occurrence of the cache event. Other embodiments are described and claimed.

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