公开(公告)号：US10216616B2

公开(公告)日：2019-02-26

申请号：US15201405

申请日：2016-07-02

申请人： Intel Corporation

发明人： Beeman C. Strong ,  Matthew C. Merten ,  Lee W. Baugh

IPC分类号： G06F11/36 ,  G06F9/30 ,  G06F12/0875 ,  G06F9/38 ,  G06F11/34

摘要： A processor is disclosed and comprises a front end including circuitry to decode instructions from an instruction stream; a data cache unit including circuitry to cache data for the processor; and a core triggering block (CTB) to provide integration between two or more different debug capabilities.

公开(公告)号：US20180004628A1

公开(公告)日：2018-01-04

申请号：US15201405

申请日：2016-07-02

申请人： Intel Corporation

发明人： Beeman C. Strong ,  Matthew C. Merten ,  Lee W. Baugh

IPC分类号： G06F11/36 ,  G06F9/30 ,  G06F12/0875

CPC分类号： G06F11/3648 ,  G06F9/3004 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/3877 ,  G06F11/3476 ,  G06F11/3636 ,  G06F12/0875 ,  G06F2212/452

摘要： There is disclosed in an example a processor, having: a front end including circuitry to decode instructions from an instruction stream; a data cache unit including circuitry to cache data for the processor; and a core triggering block (CTB) to provide integration between two or more different debug capabilities.

公开(公告)号：US20190188115A1

公开(公告)日：2019-06-20

申请号：US16284581

申请日：2019-02-25

申请人： Intel Corporation

发明人： Beeman C. Strong ,  Matthew C. Merten ,  Lee W. Baugh

IPC分类号： G06F11/36 ,  G06F9/30 ,  G06F9/38 ,  G06F12/0875

CPC分类号： G06F11/3648 ,  G06F9/3004 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/3877 ,  G06F11/3476 ,  G06F11/3636 ,  G06F12/0875 ,  G06F2212/452

摘要： There is disclosed in an example a processor, having: a front end including circuitry to decode instructions from an instruction stream; a data cache unit including circuitry to cache data for the processor; and a core triggering block (CTB) to provide integration between two or more different debug capabilities.