知搜-全球专利检索

  1. 登录
  2. 注册

搜索结果

8 条记录 (耗时 0.018 秒)

    SRAM storage unit based on DICE structure
    1.
    发明授权
    SRAM storage unit based on DICE structure 有权
    基于DICE结构的SRAM存储单元

    公开(公告)号：US09536585B2

    公开(公告)日：2017-01-03

    申请号：US14904979

    申请日：2014-05-28

    申请人： Institute of Microelectronics, Chinese Academy of Sciences

    发明人： Mengxin Liu ,  Xin Liu ,  Fazhan Zhao ,  Zhengsheng Han

    IPC分类号： G11C11/34 ,  G11C11/419

    CPC分类号： G11C11/34 ,  G11C11/412 ,  G11C11/419

    摘要： The present invention provides an improved SRAM memory cell based on a DICE structure, which comprises following structures: four inverter structures formed through arranging PMOS transistors and NMOS transistors in series, wherein the part between the drains of a PMOS transistor and an NMOS transistor serves as a storage node; each storage node controls the gate voltage of an NMOS transistor of the other inverter structure and of a PMOS transistor of another inverter structure; a transmission structure consisting of four NMOS transistors, whose source, gate and drain are respectively connected with a bit line/bit bar line, a word line and a storage node. The use of an improved SRAM memory cell based on a DICE structure not only avoids such defects as small static noise margin and being prone to transmission error facing the traditional cell structures consisting of 6 transistors, but also resolves the problem that the current SRAM storage cells based on a DICE structure can easily be affected by the electrical level of storage nodes. This effectively improves reliability of storage cells.

    摘要翻译： 本发明提供了一种基于DICE结构的改进的SRAM存储单元，其包括以下结构：通过串联布置PMOS晶体管和NMOS晶体管而形成的四个反相器结构，其中PMOS晶体管的漏极和NMOS晶体管之间的部分用作 存储节点; 每个存储节点控制另一个逆变器结构的NMOS晶体管的栅极电压和另一个反相器结构的PMOS晶体管的栅极电压; 由四个NMOS晶体管组成的传输结构，其源极，栅极和漏极分别与位线/位线条，字线和存储节点连接。 基于DICE结构的改进的SRAM存储单元的使用不仅避免了由6个晶体管组成的传统单元结构面临的小静态噪声容限和易发生传输错误等缺陷，而且解决了当前SRAM存储单元 基于DICE结构可以容易地受到存储节点电平的影响。 这有效地提高了存储单元的可靠性。

    FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURING THE SAME
    2.
    发明申请
    FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURING THE SAME 审中-公开
    场效应晶体管及其制造方法

    公开(公告)号：US20140239385A1

    公开(公告)日：2014-08-28

    申请号：US14346223

    申请日：2012-09-21

    申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

    发明人： Jinshun Bi ,  Chaohe Hai ,  Zhengsheng Han ,  Jiajun Luo

    IPC分类号： H01L29/78 ,  H01L29/66

    CPC分类号： H01L29/7835 ,  H01L21/2815 ,  H01L29/66666 ,  H01L29/7827

    摘要： A Field Effect Transistor (FET) and a method of manufacturing the same are provided. The FET may include a substrate; a source and a drain, one of which is formed on a bulge formed on a top surface of the substrate, and the other of which is formed in the substrate below but laterally offset from the bulge; a gate formed at a position where the bulge and the top surface of the substrate join each other; and a gate dielectric layer formed between the gate and the bulge and also between the gate and the top surface of the substrate. The FET has a vertical configuration, where the source is disposed on top of the bulge while the drain is disposed in the substrate, that is, the source and the drain are not in one same plane. As a result, the FET may have its area significantly reduced. Therefore, it is possible to improve an integration density of an IC and thus reduce cost.

    摘要翻译： 提供场效应晶体管（FET）及其制造方法。 FET可以包括衬底; 源极和漏极，其中一个形成在形成在基板的顶表面上的凸起上，另一个形成在基板的下方但横向偏离凸起; 形成在所述凸起和所述基板的上表面的位置的栅极彼此连接的栅极; 以及在栅极和凸起之间以及栅极和衬底的顶表面之间形成的栅极电介质层。 FET具有垂直配置，其中源设置在凸起的顶部，而漏极设置在衬底中，即源极和漏极不在同一平面中。 结果，FET可能使其面积显着降低。 因此，可以提高IC的集成密度，从而降低成本。

    SOI MOS device modeling method
    3.
    发明授权
    SOI MOS device modeling method 有权

    公开(公告)号：US09626467B2

    公开(公告)日：2017-04-18

    申请号：US14415275

    申请日：2012-09-21

    申请人： Institute of Microelectronics, Chinese Academy of Sciences

    发明人： Jianhui Bu ,  Jinshun Bi ,  Jiajun Luo ,  Zhengsheng Han

    IPC分类号： G06F17/50 ,  H01L29/417 ,  H01L29/78

    CPC分类号： G06F17/5036 ,  H01L29/41758 ,  H01L29/78

    摘要： The present invention provides a SOI MOS device modeling method. The SOI MOS device is one having a source-drain injection not reaching the bottom. The method comprises: a) establishing an overall model comprising a primary MOS device model simulating an SOI MOS device having the source-drain injection reaching the bottom, a source body PN junction bottom capacitance model simulating a source body PN junction bottom capacitance, and a drain body PN junction bottom capacitance model simulating a drain body PN junction bottom capacitance; and b) extracting parameters respectively for the primary MOS device model, the source body PN junction bottom capacitance model, and the drain body PN junction bottom capacitance model in the overall model. In the prior art, the source body junction bottom capacitance and the drain body junction bottom capacitance in the SOI MOS device having a source-drain injection not reaching the bottom affect the performances of the device. The modeling method of the present invention takes the effect into consideration, improves model precision, and can be effectively used for the simulation design of a device.

    IMPROVED SRAM STORAGE UNIT BASED ON DICE STRUCTURE
    6.
    发明申请
    IMPROVED SRAM STORAGE UNIT BASED ON DICE STRUCTURE 有权
    基于数字结构改进的SRAM存储单元

    公开(公告)号：US20160260474A1

    公开(公告)日：2016-09-08

    申请号：US14904979

    申请日：2014-05-28

    申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

    发明人： Mengxin Liu ,  Xin Liu ,  Fazhan Zhao ,  Zhengsheng Han

    IPC分类号： G11C11/419

    CPC分类号： G11C11/34 ,  G11C11/412 ,  G11C11/419

    摘要： The present invention provides an improved SRAM memory cell based on a DICE structure, which comprises following structures: four inverter structures formed through arranging PMOS transistors and NMOS transistors in series, wherein the part between the drains of a PMOS transistor and an NMOS transistor serves as a storage node; each storage node controls the gate voltage of an NMOS transistor of the other inverter structure and of a PMOS transistor of another inverter structure; a transmission structure consisting of four NMOS transistors, whose source, gate and drain are respectively connected with a bit line/bit bar line, a word line and a storage node. The use of an improved SRAM memory cell based on a DICE structure not only avoids such defects as small static noise margin and being prone to transmission error facing the traditional cell structures consisting of 6 transistors, but also resolves the problem that the current SRAM storage cells based on a DICE structure can easily be affected by the electrical level of storage nodes. This effectively improves reliability of storage cells.

    摘要翻译： 本发明提供了一种基于DICE结构的改进的SRAM存储单元，其包括以下结构：通过串联布置PMOS晶体管和NMOS晶体管而形成的四个反相器结构，其中PMOS晶体管的漏极和NMOS晶体管之间的部分用作 存储节点; 每个存储节点控制另一个逆变器结构的NMOS晶体管的栅极电压和另一个反相器结构的PMOS晶体管的栅极电压; 由四个NMOS晶体管组成的传输结构，其源极，栅极和漏极分别与位线/位线条，字线和存储节点连接。 基于DICE结构的改进的SRAM存储单元的使用不仅避免了由6个晶体管组成的传统单元结构面临的小静态噪声容限和易发生传输错误等缺陷，而且解决了当前SRAM存储单元 基于DICE结构可以容易地受到存储节点电平的影响。 这有效地提高了存储单元的可靠性。

    METHOD FOR DETERMINING PN JUNCTION DEPTH
    7.
    发明申请
    METHOD FOR DETERMINING PN JUNCTION DEPTH 审中-公开
    确定PN结深度的方法

    公开(公告)号：US20150177312A1

    公开(公告)日：2015-06-25

    申请号：US14407170

    申请日：2012-09-21

    申请人： Institute of Microelectronics, Chinese Academy of Sciences

    发明人： Jianhui Bu ,  Jinshun Bi ,  Jiajun Luo ,  Zhengsheng Han

    IPC分类号： G01R31/26 ,  G01N27/04

    CPC分类号： G01R31/2648 ,  G01N27/041 ,  H01L22/14

    摘要： The present invention provides a method for determining PN junction depth comprising: a) measuring a square resistance in a well region; b) forming a junction type field effect transistor in the well region, changing a gate electrode voltage and measuring a source-drain resistance; c) calculating the PN junction depth according to the measured square resistance, source-drain resistance and related process parameters of the junction type field effect transistor. As compared with the prior art, the technical solution in this invention determines the PN junction depth by electrical measurement, is thus simple and feasible, and has better repeatability.

    摘要翻译： 本发明提供了一种用于确定PN结深度的方法，包括：a）测量阱区中的平方电阻; b）在阱区中形成结型场效应晶体管，改变栅极电压并测量源极 - 漏极电阻; c）根据测得的方形电阻，源极漏极电阻和结型场效应晶体管的相关工艺参数计算PN结深度。 与现有技术相比，本发明的技术方案通过电测量确定PN结深度，因此简单可行，具有更好的重复性。