公开(公告)号：US10211329B2

公开(公告)日：2019-02-19

申请号：US15184032

申请日：2016-06-16

Applicant: Infineon Technologies Americas Corp.

Inventor： Hyeongnam Kim ,  Mohamed Imam ,  Alain Charles ,  Jianwei Wan ,  Mihir Tungare ,  Chan Kyung Choi

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/41 ,  H01L29/205 ,  H01L29/417 ,  H01L29/423 ,  H01L29/43 ,  H01L29/06

Abstract: There are disclosed herein various implementations of a charge trapping prevention III-Nitride transistor. Such a transistor may be a III-Nitride high electron mobility transistor (HEMT) including a III-Nitride intermediate body situated over a substrate, a channel layer situated over the III-Nitride intermediate body, and a barrier layer situated over the channel layer. The channel layer and the barrier layer are configured to produce a two-dimensional electron gas (2DEG). In addition, the III-Nitride transistor includes a dielectric layer situated over the barrier layer, a gate coupled to the barrier layer, and a drain electrode and a source electrode each extending through the dielectric layer. The drain electrode makes ohmic contact with one or both of the barrier layer and a charge trapping prevention layer situated between the dielectric layer and the barrier layer.

公开(公告)号：US20170365701A1

公开(公告)日：2017-12-21

申请号：US15184032

申请日：2016-06-16

Applicant: Infineon Technologies Americas Corp.

Inventor： Hyeongnam Kim ,  Mohamed Imam ,  Alain Charles ,  Jianwei Wan ,  Mihir Tungare ,  Chan Kyung Choi

IPC: H01L29/778 ,  H01L29/417 ,  H01L29/205 ,  H01L29/423 ,  H01L29/20

CPC classification number: H01L29/7787 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41775 ,  H01L29/42356 ,  H01L29/432 ,  H01L29/7786

Abstract: There are disclosed herein various implementations of a charge trapping prevention III-Nitride transistor. Such a transistor may be a III-Nitride high electron mobility transistor (HEMT) including a III-Nitride intermediate body situated over a substrate, a channel layer situated over the III-Nitride intermediate body, and a barrier layer situated over the channel layer. The channel layer and the barrier layer are configured to produce a two-dimensional electron gas (2DEG). In addition, the III-Nitride transistor includes a dielectric layer situated over the barrier layer, a gate coupled to the barrier layer, and a drain electrode and a source electrode each extending through the dielectric layer. The drain electrode makes ohmic contact with one or both of the barrier layer and a charge trapping prevention layer situated between the dielectric layer and the barrier layer.

公开(公告)号：US09461034B2

公开(公告)日：2016-10-04

申请号：US14728754

申请日：2015-06-02

Applicant: Infineon Technologies Americas Corp.

Inventor： Yang Pan ,  Mohamed Imam

IPC: H01L27/02 ,  H01L29/78 ,  H01L27/06 ,  H01L29/20 ,  H01L29/16 ,  H01L29/778 ,  H01L23/538 ,  H01L29/861 ,  H01L21/768 ,  H01L21/8258 ,  H01L27/07 ,  H01L27/085 ,  H01L29/10 ,  H01L29/267

CPC classification number: H01L27/027 ,  H01L21/76898 ,  H01L21/8258 ,  H01L23/481 ,  H01L27/0248 ,  H01L27/0266 ,  H01L27/0617 ,  H01L27/0629 ,  H01L27/0694 ,  H01L27/0727 ,  H01L27/085 ,  H01L29/1075 ,  H01L29/2003 ,  H01L29/267 ,  H01L29/66666 ,  H01L29/7786 ,  H01L29/7827 ,  H01L29/8611 ,  H01L29/8616 ,  H01L2924/0002 ,  H03K17/063 ,  H03K17/6871 ,  H03K2017/6875 ,  H03K2217/0018 ,  H01L2924/00

Abstract: There are disclosed herein various implementations of a group III-V composite transistor having a switched substrate. Such a group III-V composite transistor includes a composite field-effect transistor (FET) including a depletion mode group III-V high electron mobility transistor (HEMT) situated over a substrate. The depletion mode group III-V HEMT is cascoded with an enhancement mode group IV FET to produce the composite FET. The group III-V composite transistor also includes a transistor configured to selectably couple the substrate of the depletion mode group III-V HEMT to ground and to selectably decouple the substrate from ground. That transistor is configured to ground the substrate when the depletion mode group III-V HEMT is in an off-state and to cause the substrate to float when the depletion mode group III-V HEMT is in an on-state.

Abstract translation: 这里公开了具有开关衬底的III-V族复合晶体管的各种实施方式。 这种III-V族复合晶体管包括包含位于衬底上的耗尽型组III-V高电子迁移率晶体管（HEMT）的复合场效应晶体管（FET）。 耗尽模式组III-V HEMT与增强模式组IV FET串联以产生复合FET。 III-V族复合晶体管还包括晶体管，其被配置为将耗尽模式组III-V HEMT的衬底可选地耦合到地，并且可选择地将衬底与地耦合。 当耗尽模式组III-V HEMT处于断开状态时，该晶体管被配置为对衬底进行接地，并且当耗尽模式组III-V HEMT处于导通状态时，使衬底浮动。