公开(公告)号：US09608075B1

公开(公告)日：2017-03-28

申请号：US15173263

申请日：2016-06-03

Applicant: Infineon Technologies Americas Corp.

Inventor： Jianwei Wan ,  Mihir Tungare ,  Peter Kim ,  Seong-Eun Park ,  Scott Nelson ,  Srinivasan Kannan

IPC: H01L29/66 ,  H01L29/205 ,  H01L29/20 ,  H01L29/207 ,  H01L21/02 ,  H01L29/778

CPC classification number: H01L29/7786 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/0254 ,  H01L21/02579 ,  H01L21/02581 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/36

Abstract: A compound semiconductor device includes a first III-nitride buffer layer doped with carbon and/or iron, a second III-nitride buffer layer above the first III-nitride buffer layer and doped with carbon and/or iron, a first III-nitride device layer above the second III-nitride buffer layer, and a second III-nitride device layer above the first III-nitride device layer and having a different band gap than the first III-nitride device layer. A two-dimensional charge carrier gas arises along an interface between the first and second III-nitride device layers. The first III-nitride buffer layer has an average doping concentration of carbon and/or iron which is greater than that of the second III-nitride buffer layer. The second III-nitride buffer layer has an average doping concentration of carbon and/or iron which is comparable to or greater than that of the first III-nitride device layer. A method of manufacturing the compound semiconductor device is described.

公开(公告)号：US10211329B2

公开(公告)日：2019-02-19

申请号：US15184032

申请日：2016-06-16

Applicant: Infineon Technologies Americas Corp.

Inventor： Hyeongnam Kim ,  Mohamed Imam ,  Alain Charles ,  Jianwei Wan ,  Mihir Tungare ,  Chan Kyung Choi

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/41 ,  H01L29/205 ,  H01L29/417 ,  H01L29/423 ,  H01L29/43 ,  H01L29/06

Abstract: There are disclosed herein various implementations of a charge trapping prevention III-Nitride transistor. Such a transistor may be a III-Nitride high electron mobility transistor (HEMT) including a III-Nitride intermediate body situated over a substrate, a channel layer situated over the III-Nitride intermediate body, and a barrier layer situated over the channel layer. The channel layer and the barrier layer are configured to produce a two-dimensional electron gas (2DEG). In addition, the III-Nitride transistor includes a dielectric layer situated over the barrier layer, a gate coupled to the barrier layer, and a drain electrode and a source electrode each extending through the dielectric layer. The drain electrode makes ohmic contact with one or both of the barrier layer and a charge trapping prevention layer situated between the dielectric layer and the barrier layer.

公开(公告)号：US20230093855A1

公开(公告)日：2023-03-30

申请号：US18073780

申请日：2022-12-02

Applicant: Infineon Technologies Americas Corp.

Inventor： Mihir Tungare ,  Peter Kim ,  Jianwei Wan ,  Chankyung Choi

IPC: C30B25/12 ,  C30B25/18 ,  C30B29/40 ,  C30B29/06 ,  C23C16/30 ,  C23C16/458 ,  H01L21/02 ,  H01L21/683 ,  H01L21/687

Abstract: A wafer carrier includes a pocket sized and shaped to accommodate a wafer, the pocket having a base and a substantially circular perimeter, and a removable orientation marker, the removable orientation marker comprising an outer surface and an inner surface, the outer surface having an arcuate form sized and shaped to mate with the substantially circular perimeter of the pocket, and the inner surface comprising a flat face, wherein the removable orientation marker further comprises a notch at a first end of the flat face.

公开(公告)号：US20210010159A1

公开(公告)日：2021-01-14

申请号：US17030727

申请日：2020-09-24

Applicant: Infineon Technologies Americas Corp.

Inventor： Mihir Tungare ,  Peter Kim ,  Jianwei Wan ,  Chankyung Choi

IPC: C30B25/12 ,  C30B25/18 ,  C30B29/40 ,  C30B29/06 ,  C23C16/30 ,  C23C16/458 ,  H01L21/02 ,  H01L21/683 ,  H01L21/687

Abstract: A wafer carrier includes a pocket sized and shaped to accommodate a wafer, the pocket having a base and a substantially circular perimeter, and a removable orientation marker, the removable orientation marker comprising an outer surface and an inner surface, the outer surface having an arcuate form sized and shaped to mate with the substantially circular perimeter of the pocket, and the inner surface comprising a flat face, wherein the removable orientation marker further comprises a notch at a first end of the flat face.

公开(公告)号：US09728610B1

公开(公告)日：2017-08-08

申请号：US15017268

申请日：2016-02-05

Applicant: Infineon Technologies Americas Corp.

Inventor： Jianwei Wan ,  Scott Nelson ,  Srinivasan Kannan ,  Peter Kim

IPC: H01L21/338 ,  H01L29/732 ,  H01L31/109 ,  H01L29/205 ,  H01L29/20 ,  H01L29/778 ,  H01L31/0304 ,  H01L31/18 ,  H01L33/00 ,  H01L33/12 ,  H01L33/32 ,  H01S5/323 ,  H01L21/02

CPC classification number: H01L29/205 ,  H01L21/02458 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/778 ,  H01L29/7786 ,  H01L31/03044 ,  H01L31/109 ,  H01L31/1856 ,  H01L33/0025 ,  H01L33/007 ,  H01L33/0075 ,  H01L33/12 ,  H01L33/32 ,  H01S5/32341

Abstract: There are disclosed herein various implementations of a semiconductor component with a multi-layered nucleation body and method for its fabrication. The semiconductor component includes a substrate, a nucleation body situated over the substrate, and a group III-V semiconductor device situated over the nucleation body. The nucleation body includes a bottom layer formed at a low growth temperature, and a top layer formed at a high growth temperature. The nucleation body also includes an intermediate layer that is formed substantially continuously using a varying intermediate growth temperature.

公开(公告)号：US10829866B2

公开(公告)日：2020-11-10

申请号：US15477313

申请日：2017-04-03

Applicant: Infineon Technologies Americas Corp.

Inventor： Mihir Tungare ,  Peter Kim ,  Jianwei Wan ,  Chankyung Choi

IPC: C30B25/12 ,  C30B25/18 ,  C30B29/40 ,  C30B29/06 ,  C23C16/30 ,  C23C16/458 ,  H01L21/02 ,  H01L21/683 ,  H01L21/687 ,  H01L23/544

Abstract: In an embodiment, a wafer carrier includes a pocket sized and shaped to accommodate a wafer, the pocket being defined by a base and a substantially circular perimeter including an inner face and an outer face. The substantially circular perimeter includes a notch in the inner face.

公开(公告)号：US20180282899A1

公开(公告)日：2018-10-04

申请号：US15477313

申请日：2017-04-03

Applicant: Infineon Technologies Americas Corp.

Inventor： Mihir Tungare ,  Peter Kim ,  Jianwei Wan ,  Chankyung Choi

IPC: C30B25/12 ,  C30B25/18 ,  C30B29/40 ,  C30B29/06 ,  C23C16/30 ,  C23C16/458 ,  H01L21/02

Abstract: In an embodiment, a wafer carrier includes a pocket sized and shaped to accommodate a wafer, the pocket being defined by a base and a substantially circular perimeter including an inner face and an outer face. The substantially circular perimeter includes a notch in the inner face.

公开(公告)号：US11535952B2

公开(公告)日：2022-12-27

申请号：US17030727

申请日：2020-09-24

Applicant: Infineon Technologies Americas Corp.

Inventor： Mihir Tungare ,  Peter Kim ,  Jianwei Wan ,  Chankyung Choi

IPC: C30B25/12 ,  C30B25/18 ,  C30B29/40 ,  C30B29/06 ,  C23C16/30 ,  C23C16/458 ,  H01L21/02 ,  H01L21/683 ,  H01L21/687 ,  H01L23/544 ,  C30B25/02

Abstract: A wafer carrier includes a pocket sized and shaped to accommodate a wafer, the pocket having a base and a substantially circular perimeter, and a removable orientation marker, the removable orientation marker comprising an outer surface and an inner surface, the outer surface having an arcuate form sized and shaped to mate with the substantially circular perimeter of the pocket, and the inner surface comprising a flat face, wherein the removable orientation marker further comprises a notch at a first end of the flat face.

公开(公告)号：US20170365701A1

公开(公告)日：2017-12-21

申请号：US15184032

申请日：2016-06-16

Applicant: Infineon Technologies Americas Corp.

Inventor： Hyeongnam Kim ,  Mohamed Imam ,  Alain Charles ,  Jianwei Wan ,  Mihir Tungare ,  Chan Kyung Choi

IPC: H01L29/778 ,  H01L29/417 ,  H01L29/205 ,  H01L29/423 ,  H01L29/20

CPC classification number: H01L29/7787 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41775 ,  H01L29/42356 ,  H01L29/432 ,  H01L29/7786

Abstract: There are disclosed herein various implementations of a charge trapping prevention III-Nitride transistor. Such a transistor may be a III-Nitride high electron mobility transistor (HEMT) including a III-Nitride intermediate body situated over a substrate, a channel layer situated over the III-Nitride intermediate body, and a barrier layer situated over the channel layer. The channel layer and the barrier layer are configured to produce a two-dimensional electron gas (2DEG). In addition, the III-Nitride transistor includes a dielectric layer situated over the barrier layer, a gate coupled to the barrier layer, and a drain electrode and a source electrode each extending through the dielectric layer. The drain electrode makes ohmic contact with one or both of the barrier layer and a charge trapping prevention layer situated between the dielectric layer and the barrier layer.

公开(公告)号：US20170229548A1

公开(公告)日：2017-08-10

申请号：US15017268

申请日：2016-02-05

Applicant: Infineon Technologies Americas Corp.

Inventor： Jianwei Wan ,  Scott Nelson ,  Srinivasan Kannan ,  Peter Kim

IPC: H01L29/205 ,  H01L29/778 ,  H01L31/109 ,  H01L31/0304 ,  H01L21/02 ,  H01L33/00 ,  H01L33/12 ,  H01L33/32 ,  H01S5/323 ,  H01L29/20 ,  H01L31/18

CPC classification number: H01L29/205 ,  H01L21/02458 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/778 ,  H01L29/7786 ,  H01L31/03044 ,  H01L31/109 ,  H01L31/1856 ,  H01L33/0025 ,  H01L33/007 ,  H01L33/0075 ,  H01L33/12 ,  H01L33/32 ,  H01S5/32341

Abstract: There are disclosed herein various implementations of a semiconductor component with a multi-layered nucleation body and method for its fabrication. The semiconductor component includes a substrate, a nucleation body situated over the substrate, and a group III-V semiconductor device situated over the nucleation body. The nucleation body includes a bottom layer formed at a low growth temperature, and a top layer formed at a high growth temperature. The nucleation body also includes an intermediate layer that is formed substantially continuously using a varying intermediate growth temperature.