公开(公告)号：US09728610B1

公开(公告)日：2017-08-08

申请号：US15017268

申请日：2016-02-05

Applicant: Infineon Technologies Americas Corp.

Inventor： Jianwei Wan ,  Scott Nelson ,  Srinivasan Kannan ,  Peter Kim

IPC: H01L21/338 ,  H01L29/732 ,  H01L31/109 ,  H01L29/205 ,  H01L29/20 ,  H01L29/778 ,  H01L31/0304 ,  H01L31/18 ,  H01L33/00 ,  H01L33/12 ,  H01L33/32 ,  H01S5/323 ,  H01L21/02

CPC classification number: H01L29/205 ,  H01L21/02458 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/778 ,  H01L29/7786 ,  H01L31/03044 ,  H01L31/109 ,  H01L31/1856 ,  H01L33/0025 ,  H01L33/007 ,  H01L33/0075 ,  H01L33/12 ,  H01L33/32 ,  H01S5/32341

Abstract: There are disclosed herein various implementations of a semiconductor component with a multi-layered nucleation body and method for its fabrication. The semiconductor component includes a substrate, a nucleation body situated over the substrate, and a group III-V semiconductor device situated over the nucleation body. The nucleation body includes a bottom layer formed at a low growth temperature, and a top layer formed at a high growth temperature. The nucleation body also includes an intermediate layer that is formed substantially continuously using a varying intermediate growth temperature.

公开(公告)号：US09761672B1

公开(公告)日：2017-09-12

申请号：US15057985

申请日：2016-03-01

Applicant: Infineon Technologies Americas Corp.

Inventor： Scott Nelson ,  Srinivasan Kannan

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/02 ,  H01L29/205 ,  H01L29/20 ,  H01L29/778 ,  H01L33/32 ,  H01L33/00 ,  H01L33/12 ,  H01L31/109 ,  H01L31/0304 ,  H01S5/323

CPC classification number: H01L29/205 ,  H01L21/02381 ,  H01L21/02439 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/778 ,  H01L29/7786 ,  H01L31/03044 ,  H01L31/109 ,  H01L33/0025 ,  H01L33/12 ,  H01L33/32 ,  H01S5/32341

Abstract: There are disclosed herein various implementations of a semiconductor component including one or more aluminum silicon nitride layers. The semiconductor component includes a substrate, a group III-V intermediate body situated over the substrate, a group III-V buffer layer situated over the group III-V intermediate body, and a group III-V device fabricated over the group III-V buffer layer. The group III-V intermediate body includes the one or more aluminum silicon nitride layers.

公开(公告)号：US20170256618A1

公开(公告)日：2017-09-07

申请号：US15057985

申请日：2016-03-01

Applicant: Infineon Technologies Americas Corp.

Inventor： Scott Nelson ,  Srinivasan Kannan

IPC: H01L29/205 ,  H01L29/778 ,  H01L33/32 ,  H01S5/323 ,  H01L33/12 ,  H01L31/109 ,  H01L31/0304 ,  H01L29/20 ,  H01L33/00

CPC classification number: H01L29/205 ,  H01L21/02381 ,  H01L21/02439 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/778 ,  H01L29/7786 ,  H01L31/03044 ,  H01L31/109 ,  H01L33/0025 ,  H01L33/12 ,  H01L33/32 ,  H01S5/32341

Abstract: There are disclosed herein various implementations of a semiconductor component including one or more aluminum silicon nitride layers. The semiconductor component includes a substrate, a group III-V intermediate body situated over the substrate, a group III-V buffer layer situated over the group III-V intermediate body, and a group III-V device fabricated over the group III-V buffer layer. The group III-V intermediate body includes the one or more aluminum silicon nitride layers.

公开(公告)号：US09741841B2

公开(公告)日：2017-08-22

申请号：US15097636

申请日：2016-04-13

Applicant: Infineon Technologies Americas Corp.

Inventor： Scott Nelson ,  Ronald H. Birkhahn ,  Brett Hughes

IPC: H01L29/778 ,  H01L21/02 ,  H01L29/20 ,  H01L29/66 ,  H01L29/205

CPC classification number: H01L29/7787 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462

Abstract: According to one exemplary embodiment, a group III-V semiconductor device includes at least one transition layer situated over a substrate. The group III-V semiconductor device further includes a first strain-relieving interlayer situated over the at least one transition layer and a second strain-relieving interlayer situated over the first strain-relieving interlayer. The group III-V semiconductor device further includes a first group III-V semiconductor body situated over the second strain-relieving interlayer. The first and second strain-relieving interlayers comprise different semiconductor materials so as to reduce a strain in the first group III-V semiconductor body. The second strain-relieving interlayer can be substantially thinner than the first strain-relieving interlayer.

公开(公告)号：US20170229548A1

公开(公告)日：2017-08-10

申请号：US15017268

申请日：2016-02-05

Applicant: Infineon Technologies Americas Corp.

Inventor： Jianwei Wan ,  Scott Nelson ,  Srinivasan Kannan ,  Peter Kim

IPC: H01L29/205 ,  H01L29/778 ,  H01L31/109 ,  H01L31/0304 ,  H01L21/02 ,  H01L33/00 ,  H01L33/12 ,  H01L33/32 ,  H01S5/323 ,  H01L29/20 ,  H01L31/18

CPC classification number: H01L29/205 ,  H01L21/02458 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/778 ,  H01L29/7786 ,  H01L31/03044 ,  H01L31/109 ,  H01L31/1856 ,  H01L33/0025 ,  H01L33/007 ,  H01L33/0075 ,  H01L33/12 ,  H01L33/32 ,  H01S5/32341

Abstract: There are disclosed herein various implementations of a semiconductor component with a multi-layered nucleation body and method for its fabrication. The semiconductor component includes a substrate, a nucleation body situated over the substrate, and a group III-V semiconductor device situated over the nucleation body. The nucleation body includes a bottom layer formed at a low growth temperature, and a top layer formed at a high growth temperature. The nucleation body also includes an intermediate layer that is formed substantially continuously using a varying intermediate growth temperature.

公开(公告)号：US20160233327A1

公开(公告)日：2016-08-11

申请号：US15097636

申请日：2016-04-13

Applicant: Infineon Technologies Americas Corp.

Inventor： Scott Nelson ,  Ronald H. Birkhahn ,  Brett Hughes

IPC: H01L29/778 ,  H01L21/02 ,  H01L29/66 ,  H01L29/20 ,  H01L29/205

CPC classification number: H01L29/7787 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462

Abstract: According to one exemplary embodiment, a group III-V semiconductor device includes at least one transition layer situated over a substrate. The group III-V semiconductor device further includes a first strain-relieving interlayer situated over the at least one transition layer and a second strain-relieving interlayer situated over the first strain-relieving interlayer. The group III-V semiconductor device further includes a first group III-V semiconductor body situated over the second strain-relieving interlayer. The first and second strain-relieving interlayers comprise different semiconductor materials so as to reduce a strain in the first group III-V semiconductor body. The second strain-relieving interlayer can be substantially thinner than the first strain-relieving interlayer.

Abstract translation: 根据一个示例性实施例，III-V族半导体器件包括位于衬底上方的至少一个过渡层。 III-V族半导体器件还包括位于至少一个过渡层上的第一应变消除中间层和位于第一应变消除中间层上方的第二应变消除中间层。 III-V族半导体器件还包括位于第二应变消除中间层上的第一III-V族半导体体。 第一和第二应变消除中间层包括不同的半导体材料，以便减小第一组III-V半导体体的应变。 第二应变消除中间层可以比第一应变消除中间层更薄。

公开(公告)号：US09608075B1

公开(公告)日：2017-03-28

申请号：US15173263

申请日：2016-06-03

Applicant: Infineon Technologies Americas Corp.

Inventor： Jianwei Wan ,  Mihir Tungare ,  Peter Kim ,  Seong-Eun Park ,  Scott Nelson ,  Srinivasan Kannan

IPC: H01L29/66 ,  H01L29/205 ,  H01L29/20 ,  H01L29/207 ,  H01L21/02 ,  H01L29/778

CPC classification number: H01L29/7786 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/0254 ,  H01L21/02579 ,  H01L21/02581 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/36

Abstract: A compound semiconductor device includes a first III-nitride buffer layer doped with carbon and/or iron, a second III-nitride buffer layer above the first III-nitride buffer layer and doped with carbon and/or iron, a first III-nitride device layer above the second III-nitride buffer layer, and a second III-nitride device layer above the first III-nitride device layer and having a different band gap than the first III-nitride device layer. A two-dimensional charge carrier gas arises along an interface between the first and second III-nitride device layers. The first III-nitride buffer layer has an average doping concentration of carbon and/or iron which is greater than that of the second III-nitride buffer layer. The second III-nitride buffer layer has an average doping concentration of carbon and/or iron which is comparable to or greater than that of the first III-nitride device layer. A method of manufacturing the compound semiconductor device is described.