公开(公告)号：US10790369B2

公开(公告)日：2020-09-29

申请号：US16050230

申请日：2018-07-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Vibhor Jain ,  Qizhi Liu ,  John J. Pekarik

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L29/812 ,  H01L29/49 ,  H01L29/47 ,  H01L27/12 ,  H01L29/51

Abstract: A tunable breakdown voltage RF MESFET and/or MOSFET and methods of manufacture are disclosed. The method includes forming a first line and a second line on an underlying gate dielectric material. The second line has a width tuned to a breakdown voltage. The method further includes forming sidewall spacers on sidewalls of the first and second line such that the space between first and second line is pinched-off by the dielectric spacers. The method further includes forming source and drain regions adjacent outer edges of the first line and the second line, and removing at least the second line to form an opening between the sidewall spacers of the second line and to expose the underlying gate dielectric material. The method further includes depositing a layer of material on the underlying gate dielectric material within the opening, and forming contacts to a gate structure and the source and drain regions.

公开(公告)号：US09606291B2

公开(公告)日：2017-03-28

申请号：US14749907

申请日：2015-06-25

Applicant: International Business Machines Corporation

Inventor： John J. Ellis-Monaghan ,  Brendan S. Harris ,  Vibhor Jain ,  Yves T. Ngu ,  Sebastian T. Ventrone

IPC: G02B6/12 ,  G02B6/125 ,  G02B6/122 ,  G02B6/13

CPC classification number: G02B6/125 ,  G02B6/12002 ,  G02B6/1228 ,  G02B6/13 ,  G02B6/30 ,  G02B2006/12061 ,  G02B2006/12147 ,  G02B2006/12195

Abstract: Integrated optical structures include a first wafer layer, a first insulator layer directly connected to the top of the first wafer layer, a second wafer layer directly connected to the top of the first insulator layer, a second insulator layer directly connected to the top of the second wafer layer, and a third wafer layer directly connected to the top of the second insulator layer. Such structures include: a first optical waveguide positioned within the second wafer layer; an optical coupler positioned within the second wafer layer, the second insulator layer, and the third wafer layer; and a second optical waveguide positioned within the third wafer layer. The optical coupler transmits an optical beam from the first optical waveguide to the second optical waveguide through the second insulator layer.

公开(公告)号：US20150357325A1

公开(公告)日：2015-12-10

申请号：US14296812

申请日：2014-06-05

Applicant: International Business Machines Corporation

Inventor： Yan Ding ,  Vibhor Jain ,  Thomas Kessler ,  Yves T. Ngu ,  Robert M. Rassel ,  Sebastian T. Ventrone

IPC: H01L27/06 ,  H01L21/768 ,  H01L23/367 ,  H01L21/822 ,  H01L27/12 ,  H01L23/48

CPC classification number: H01L27/0694 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/3677 ,  H01L23/481 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In an approach to fabricating a silicon on insulator wafer, one or more semiconductor device elements are implanted and one or more shallow trench isolations are formed on a top surface of a first semiconductor wafer. A first dielectric material layer is deposited over the top surface of the first semiconductor wafer, filling the shallow trench isolations. A dielectric material layer on a bottom surface of a second semiconductor wafer is bonded to a dielectric material layer on the top of the first semiconductor wafer and one or more semiconductor devices are formed on a top surface of the second semiconductor wafer. Then, one or more through silicon vias are created connecting the one or more semiconductor devices on the top surface of the second semiconductor wafer and the one or more semiconductor device elements on the top surface of the first semiconductor wafer.

Abstract translation: 在制造绝缘体上硅晶片的方法中，注入一个或多个半导体器件元件，并且在第一半导体晶片的顶表面上形成一个或多个浅沟槽隔离。 在第一半导体晶片的顶表面上沉积第一介电材料层，填充浅沟槽隔离物。 在第二半导体晶片的底面上的电介质材料层与第一半导体晶片的顶部的电介质材料层接合，在第二半导体晶片的顶面上形成有一个以上的半导体装置。 然后，产生连接第二半导体晶片的顶表面上的一个或多个半导体器件和第一半导体晶片的顶表面上的一个或多个半导体器件元件的一个或多个穿过硅通孔。

公开(公告)号：US20150194510A1

公开(公告)日：2015-07-09

申请号：US14151225

申请日：2014-01-09

Applicant: International Business Machines Corporation

Inventor： Renata Camillo-Castillo ,  Peng Cheng ,  Vibhor Jain ,  Qizhi Liu ,  John J. Pekarik

IPC: H01L29/73 ,  H01L29/10 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/732 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/73 ,  H01L29/7371

Abstract: Fabrication methods, device structures, and design structures for a bipolar junction transistor. An intrinsic base layer is formed on a semiconductor substrate, an etch stop layer is formed on the intrinsic base layer, and an extrinsic base layer is formed on the etch stop layer. A trench is formed that penetrates through the extrinsic base layer to the etch stop layer. The trench is formed by etching the extrinsic base layer selective to the etch stop layer. The first trench is extended through the etch stop layer to the intrinsic base layer by etching the etch stop layer selective to the intrinsic base layer. After the trench is extended through the etch stop layer, an emitter is formed using the trench.

Abstract translation: 双极结晶体管的制造方法，器件结构和设计结构。 在半导体衬底上形成本征基极层，在本征基极层上形成蚀刻停止层，在蚀刻停止层上形成非本征基极层。 形成沟槽，其穿过外部基极层到蚀刻停止层。 通过蚀刻对蚀刻停止层选择性的非本征基层形成沟槽。 通过蚀刻对本征基极层有选择性的蚀刻停止层，第一沟槽通过蚀刻停止层延伸到本征基极层。 在沟槽延伸通过蚀刻停止层之后，使用沟槽形成发射极。

公开(公告)号：US20150035011A1

公开(公告)日：2015-02-05

申请号：US13955382

申请日：2013-07-31

Applicant: International Business Machines Corporation

Inventor： Renata Camillo-Castillo ,  Vibhor Jain ,  Vikas K. Kaushal ,  Marwan H. Khater

IPC: H01L29/737 ,  G06F17/50 ,  H01L29/66

CPC classification number: H01L29/737 ,  H01L29/0649 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/7371 ,  H01L29/7378

Abstract: Fabrication methods, device structures, and design structures for a heterojunction bipolar transistor. A trench isolation region and a collector are formed in a semiconductor substrate. The collector is coextensive with the trench isolation region. A first semiconductor layer is formed that includes a of single crystal section disposed on the collector and on the trench isolation region. A second semiconductor layer is formed that includes a single crystal section disposed on the single crystal section of the first semiconductor layer and that has an outer edge that overlies the trench isolation region. The section of the first semiconductor layer has a second width greater than a first width of the collector. The section of the second semiconductor layer has a third width greater than the second width. A cavity extends laterally from the outer edge of section of the second semiconductor layer to the section of the first semiconductor layer.

Abstract translation: 异质结双极晶体管的制造方法，器件结构和设计结构。 在半导体衬底中形成沟槽隔离区和集电极。 收集器与沟槽隔离区域共同延伸。 形成第一半导体层，其包括设置在集电极和沟槽隔离区上的单晶部分。 形成第二半导体层，其包括设置在第一半导体层的单晶部分上并具有覆盖在沟槽隔离区域上的外边缘的单晶部分。 第一半导体层的截面具有大于集电体的第一宽度的第二宽度。 第二半导体层的截面具有大于第二宽度的第三宽度。 空腔从第二半导体层的截面的外边缘横向延伸到第一半导体层的部分。

公开(公告)号：US08946861B2

公开(公告)日：2015-02-03

申请号：US13914707

申请日：2013-06-11

Applicant: International Business Machines Corporation

Inventor： Renata A. Camillo-Castillo ,  Vibhor Jain ,  Vikas K. Kaushal ,  Marwan H. Khater

IPC: H01L27/082 ,  H01L27/102 ,  H01L29/70 ,  H01L31/11 ,  H01L29/739 ,  H01L31/075 ,  H01L31/105 ,  H01L31/117 ,  H01L29/10 ,  H01L29/66 ,  H01L29/737

CPC classification number: H01L29/1004 ,  H01L29/0653 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/7371

Abstract: Disclosed are bipolar devices, which incorporate an entirely monocrystalline link-up region between the intrinsic and extrinsic base layers, and methods of forming the devices. In the methods, a selective epitaxial deposition process grows monocrystalline semiconductor material for the extrinsic base layer on an exposed edge portion of a monocrystalline section of an intrinsic base layer. This deposition process is continued to intentionally overgrow the monocrystalline semiconductor material until it grows laterally and essentially covers a dielectric landing pad on a center portion of that same monocrystalline section of the intrinsic base layer. Subsequently, an opening is formed through the extrinsic base layer to the dielectric landing pad and the dielectric landing pad is selectively removed, thereby exposing monocrystalline surfaces only of the intrinsic and extrinsic base layers. A semiconductor layer is then formed by epitaxial deposition on the exposed monocrystalline surfaces, thereby forming the entirely monocrystalline link-up region.

Abstract translation: 公开了双极器件，其在内部和外部基极层之间并入完整的单晶连接区域，以及形成器件的方法。 在该方法中，选择性外延沉积工艺在本征基底层的单晶部分的暴露边缘部分上生长外部基极层的单晶半导体材料。 该沉积过程继续有意地过度生长单晶半导体材料，直到其横向生长并且基本上覆盖本征基层的相同单晶部分的中心部分上的电介质着陆焊盘。 随后，通过外部基极层形成开口到电介质接合焊盘，并且选择性地去除电介质着陆焊盘，从而仅暴露出本征和外部基极层的单晶表面。 然后通过外延沉积在暴露的单晶表面上形成半导体层，从而形成完全单晶连接区域。

公开(公告)号：US08875064B2

公开(公告)日：2014-10-28

申请号：US13833028

申请日：2013-03-15

Applicant: International Business Machines Corporation

Inventor： Davinder Aggarwal ,  Vibhor Jain ,  Janakiraman Viraraghavan

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: Approaches for generating test cases for design rule checking are provided. A method includes extracting coordinates of an error marker in an integrated circuit design. The method also includes creating an error polygon using the coordinates. The method additionally includes selecting polygons in the design that touch the error polygon. The method further includes identifying a rectangle that encloses the selected polygons. The method also includes generating a test case based on data of the design contained within the rectangle. The extracting, the creating, the selecting, the identifying, and the generating are performed using a computer device.

Abstract translation: 提供了用于生成设计规则检查的测试用例的方法。 一种方法包括在集成电路设计中提取错误标记的坐标。 该方法还包括使用坐标创建错误多边形。 该方法还包括在设计中选择触摸误差多边形的多边形。 该方法还包括识别包围所选择的多边形的矩形。 该方法还包括基于包含在矩形内的设计的数据生成测试用例。 使用计算机设备执行提取，创建，选择，识别和生成。

公开(公告)号：US10770557B2

公开(公告)日：2020-09-08

申请号：US15982370

申请日：2018-05-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Vibhor Jain ,  Qizhi Liu ,  John J. Pekarik

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L29/812 ,  H01L29/49 ,  H01L29/47 ,  H01L27/12 ,  H01L29/51

Abstract: A tunable breakdown voltage RF MESFET and/or MOSFET and methods of manufacture are disclosed. The method includes forming a first line and a second line on an underlying gate dielectric material. The second line has a width tuned to a breakdown voltage. The method further includes forming sidewall spacers on sidewalls of the first and second line such that the space between first and second line is pinched-off by the dielectric spacers. The method further includes forming source and drain regions adjacent outer edges of the first line and the second line, and removing at least the second line to form an opening between the sidewall spacers of the second line and to expose the underlying gate dielectric material. The method further includes depositing a layer of material on the underlying gate dielectric material within the opening, and forming contacts to a gate structure and the source and drain regions.

公开(公告)号：US10109716B2

公开(公告)日：2018-10-23

申请号：US14864020

申请日：2015-09-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Vibhor Jain ,  Qizhi Liu ,  John J. Pekarik

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L29/812 ,  H01L27/12 ,  H01L29/51 ,  H01L29/49 ,  H01L29/47

Abstract: A tunable breakdown voltage RF MESFET and/or MOSFET and methods of manufacture are disclosed. The method includes forming a first line and a second line on an underlying gate dielectric material. The second line has a width tuned to a breakdown voltage. The method further includes forming sidewall spacers on sidewalls of the first and second line such that the space between first and second line is pinched-off by the dielectric spacers. The method further includes forming source and drain regions adjacent outer edges of the first line and the second line, and removing at least the second line to form an opening between the sidewall spacers of the second line and to expose the underlying gate dielectric material. The method further includes depositing a layer of material on the underlying gate dielectric material within the opening, and forming contacts to a gate structure and the source and drain regions.

公开(公告)号：US20160377806A1

公开(公告)日：2016-12-29

申请号：US14749907

申请日：2015-06-25

Applicant: International Business Machines Corporation

Inventor： John J. Ellis-Monaghan ,  Brendan S. Harris ,  Vibhor Jain ,  Yves T. Ngu ,  Sebastian T. Ventrone

IPC: G02B6/125 ,  G02B6/122 ,  G02B6/13 ,  G02B6/12

CPC classification number: G02B6/125 ,  G02B6/12002 ,  G02B6/1228 ,  G02B6/13 ,  G02B6/30 ,  G02B2006/12061 ,  G02B2006/12147 ,  G02B2006/12195

Abstract: Integrated optical structures include a first wafer layer, a first insulator layer directly connected to the top of the first wafer layer, a second wafer layer directly connected to the top of the first insulator layer, a second insulator layer directly connected to the top of the second wafer layer, and a third wafer layer directly connected to the top of the second insulator layer. Such structures include: a first optical waveguide positioned within the second wafer layer; an optical coupler positioned within the second wafer layer, the second insulator layer, and the third wafer layer; and a second optical waveguide positioned within the third wafer layer. The optical coupler transmits an optical beam from the first optical waveguide to the second optical waveguide through the second insulator layer.

Abstract translation: 集成光学结构包括第一晶片层，直接连接到第一晶片层顶部的第一绝缘体层，直接连接到第一绝缘体层顶部的第二晶体层，直接连接到第一晶体层顶部的第二绝缘体层 第二晶片层和直接连接到第二绝缘体层的顶部的第三晶片层。 这种结构包括：位于第二晶片层内的第一光波导; 位于所述第二晶片层内的光耦合器，所述第二绝缘体层和所述第三晶片层; 以及位于第三晶片层内的第二光波导。 光耦合器通过第二绝缘体层将光束从第一光波导传输到第二光波导。