公开(公告)号：US20030178649A1

公开(公告)日：2003-09-25

申请号：US10103602

申请日：2002-03-20

Applicant: International Business Machines Corporation

Inventor： Krishna Darbha ,  Miguel A. Jimarez ,  Matthew M. Reiss ,  Sanjeev B. Sathe ,  Charles G. Woychik

IPC: H01L027/10

CPC classification number: H01L23/49833 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15151 ,  H01L2924/00012

Abstract: A method and structure to electrically couple a semiconductor device to a substrate that is divided into a plurality of segments. Alternatively, a semiconductor device may be divided into a plurality of segments and the plurality of segments are electrically coupled to a single substrate.

Abstract translation: 将半导体器件电耦合到被分成多个段的衬底的方法和结构。 或者，半导体器件可以被分成多个段，并且多个段电耦合到单个衬底。

公开(公告)号：US20020108768A1

公开(公告)日：2002-08-15

申请号：US10119134

申请日：2002-04-09

Applicant: International Business Machines Corporation

Inventor： Lisa J. Jimarez ,  Miguel A. Jimarez

IPC: H01L023/02

CPC classification number: H01L23/16 ,  H01L23/36 ,  H01L23/50 ,  H01L25/0655 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/15311 ,  Y10S269/90 ,  Y10T29/49128 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49165 ,  Y10T29/49169 ,  Y10T29/49993 ,  Y10T29/53265

Abstract: A chip mounting assembly is provided which includes a dielectric substrate having at least one integrated circuit (I/C) chip mounted thereon. An electrically conductive cover plate is in contact with all the chips with an electrically non-conducting thermally conducting adhesive. A stiffener member is provided which is mounted on the substrate and laterally spaced from the integrated circuit chip. At least one electrically conductive ground pad is formed on the substrate. The stiffener has at least one through opening therein and electrically conductive adhesive extending through each opening and contacting the cover plate and each ground pad. The invention also provides a method of forming such an I/C chip assembly.

Abstract translation: 提供了一种芯片安装组件，其包括具有安装在其上的至少一个集成电路（I / C）芯片的电介质基板。 导电盖板与具有不导电导热粘合剂的所有芯片接触。 提供了一种加强件，其安装在基板上并与集成电路芯片横向间隔开。 在衬底上形成至少一个导电接地焊盘。 加强件在其中具有至少一个通孔，导电粘合剂延伸穿过每个开口并接触盖板和每个接地垫。 本发明还提供了一种形成这种I / C芯片组件的方法。

公开(公告)号：US20020096746A1

公开(公告)日：2002-07-25

申请号：US10037536

申请日：2002-01-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： David N. Cokely ,  Thomas M. Culnane ,  Lisa J. Jimarez ,  Miguel A. Jimarez ,  Li Li ,  Donald I. Mead

IPC: H01L023/495

CPC classification number: H01L24/81 ,  H01L21/6835 ,  H01L24/75 ,  H01L2224/75 ,  H01L2224/75755 ,  H01L2224/7598 ,  H01L2224/75983 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/014

Abstract: Fixtures for attaching a semiconductor chip to a substrate. The semiconductor chip has an array of joining material bumps, such as C4 solder balls. The substrate has an array of conductive pads corresponding to the array of joining material bumps. In a first embodiment the fixture has a body having a first cavity for containing the semiconductor chip and a second cavity in communication with the first cavity for containing the substrate. Whereby the substrate is placed over the semiconductor chip with the conductive pads opposing and in contact with the joining material bumps, such that during reflow of the joining material bumps, the weight of the substrate acts against the joining material bumps and aids in the attachment of the semiconductor chip to the substrate to form electrical connections therebetween. In a second embodiment the fixture has a first plate having a first opening for disposal of the semiconductor chip therein, a second plate stacked below the first plate and having a thickness substantially equal to the thickness of the substrate, the second plate further having a second opening opposing the first opening for disposal of the substrate therein, and a third plate stacked below the second plate such that the substrate is flattened in the second opening under the weight of the first plate thereby aiding in the attachment of the joining material bumps to their corresponding conductive pads during solder reflow to form electrical connections therebetween. Methods for use of the fixtures is also provided.

Abstract translation: 用于将半导体芯片附接到基板的夹具。 半导体芯片具有连接材料凸块的阵列，例如C4焊球。 衬底具有对应于接合材料凸块阵列的导电焊盘阵列。 在第一实施例中，固定装置具有主体，该主体具有用于容纳半导体芯片的第一空腔和与第一空腔连通以容纳基板的第二空腔。 由此将衬底放置在半导体芯片上，其中导电焊盘与接合材料凸块相对并接触，使得在接合材料凸块的回流期间，衬底的重量抵抗接合材料凸起并且有助于附接 半导体芯片到基板以在它们之间形成电连接。 在第二实施例中，固定装置具有第一板，其具有用于在其中处理半导体芯片的第一开口，堆叠在第一板下方并且具有基本上等于衬底厚度的厚度的第二板，第二板还具有第二板 与第一开口相对地打开以处理其中的基板;以及第三板，堆叠在第二板下方，使得基板在第一板的重量下在第二开口中变平，由此辅助将接合材料凸块附接到它们 焊料回流期间相应的导电焊盘在其间形成电连接。 还提供了使用固定装置的方法。

公开(公告)号：US20040134685A1

公开(公告)日：2004-07-15

申请号：US10744142

申请日：2003-12-22

Applicant: International Business Machines Corporation

Inventor： Kenneth Fallon ,  Miguel A. Jimarez ,  Ross W. Keesler ,  John M. Lauffer ,  Roy H. Magnuson ,  Voya R. Markovich ,  Irv Memis ,  Jim P. Paoletti ,  Marybeth Perrino ,  John A. Welsh ,  William E. Wilson

IPC: G03G009/00 ,  H05K001/11 ,  H01R012/04

CPC classification number: H05K3/445 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/056 ,  H05K1/113 ,  H05K3/0023 ,  H05K3/0052 ,  H05K3/0094 ,  H05K3/06 ,  H05K3/108 ,  H05K3/426 ,  H05K3/429 ,  H05K3/44 ,  H05K3/4623 ,  H05K3/4641 ,  H05K2201/0919 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/096 ,  H05K2201/10734 ,  H05K2203/0323 ,  H05K2203/0574 ,  H05K2203/0733 ,  H05K2203/1394 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A method of forming a printed circuit board with a metal power plane layer between two photoimageable dielectric layers is provided. Photoformed metal filled vias and plated through holes are in the photopatternable material, and signal circuitry is on the surfaces of each of the dielectric materials connected to the vias and plated through holes. A border may be around the board including a metal layer terminating in from the edge of one of the dielectric layers. Copper foil with clearance holes is provided. First and second layers of photoimageable curable dielectric material are on opposite sides of the copper. Patterns are developed on the first and second layers of the photoimageable material to reveal the metal layer through vias. Through holes are developed where holes were patterned in both dielectric layers. The surfaces of the photoimageable material, vias and through holes are metallized by copper plating, preferably using photoresist.

Abstract translation: 提供了一种在两个可光成像的电介质层之间形成具有金属功率平面层的印刷电路板的方法。 光刻图形的金属填充通孔和电镀通孔位于光图案化材料中，信号电路位于连接到通孔和电镀通孔的每个介电材料的表面上。 边界可以在板的周围，包括从一个电介质层的边缘终止的金属层。 提供带有间隙孔的铜箔。 第一层和第二层可光成像的可固化电介质材料位于铜的相对两侧。 在可光成像材料的第一层和第二层上形成图案以通过通孔显露金属层。 开发了通孔，在两个电介质层中对其进行图案化。 可光成像材料，通孔和通孔的表面通过镀铜进行金属化，优选使用光致抗蚀剂。

公开(公告)号：US20020062970A1

公开(公告)日：2002-05-30

申请号：US09727271

申请日：2000-11-30

Applicant: International Business Machines Corporation

Inventor： Lisa J. Jimarez ,  Miguel A. Jimarez

IPC: H02G003/08

CPC classification number: H01L23/16 ,  H01L23/36 ,  H01L23/50 ,  H01L25/0655 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/15311 ,  Y10S269/90 ,  Y10T29/49128 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49165 ,  Y10T29/49169 ,  Y10T29/49993 ,  Y10T29/53265

Abstract: A chip mounting assembly is provided which includes a dielectric substrate having at least one integrated circuit (I/C) chip mounted thereon. An electrically conductive cover plate is in contact with all the chips with an electrically non-conducting thermally conducting adhesive. A stiffener member is provided which is mounted on the substrate and laterally spaced from the integrated circuit chip. At least one electrically conductive ground pad is formed on the substrate. The stiffener has at least one through opening therein and electrically conductive adhesive extending through each opening and contacting the cover plate and each ground pad. The invention also provides a method of forming such an I/C chip assembly.

Abstract translation: 提供了一种芯片安装组件，其包括具有安装在其上的至少一个集成电路（I / C）芯片的电介质基板。 导电盖板与具有不导电导热粘合剂的所有芯片接触。 提供了一种加强件，其安装在基板上并与集成电路芯片横向间隔开。 在衬底上形成至少一个导电接地焊盘。 加强件在其中具有至少一个通孔，导电粘合剂延伸穿过每个开口并接触盖板和每个接地垫。 本发明还提供了一种形成这种I / C芯片组件的方法。

公开(公告)号：US20030020150A1

公开(公告)日：2003-01-30

申请号：US10251072

申请日：2002-09-19

Applicant: International Business Machines Corporation

Inventor： Lisa J. Jimarez ,  Miguel A. Jimarez ,  Voya R. Markovich ,  Cynthia S. Milkovich ,  Charles H. Perry ,  Brenda L. Peterson

IPC: H01L023/02

CPC classification number: H01L21/4857 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L2924/0002 ,  H05K1/0271 ,  H05K1/0306 ,  H05K1/113 ,  H05K3/3436 ,  H05K3/3457 ,  H05K3/4053 ,  H05K3/4069 ,  H05K3/4605 ,  H05K3/4644 ,  H05K3/4688 ,  H05K2201/0133 ,  H05K2201/015 ,  H05K2201/09436 ,  H05K2201/09509 ,  H05K2201/10734 ,  H05K2203/061 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49153 ,  Y10T29/49165 ,  H01L2924/00

Abstract: An electronic package and method of making the electronic package is provided. A layer of dielectric material is positioned on a first surface of a substrate which includes a plurality of conductive contacts. At least one through hole is formed in the layer of dielectric material in alignment with at least one of the plurality of conductive contacts. A conductive material is positioned in the at least one through hole substantially filling the through hole. At least one conductive member is positioned on the conductive material in the through hole and in electrical contact with the conductive material. The electronic package improves field operating life of an assembly which includes a semiconductor chip attached to a second surface of the substrate and a printed wiring board attached to the conductive members.

公开(公告)号：US20010018230A1

公开(公告)日：2001-08-30

申请号：US09782471

申请日：2001-02-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Miguel A. Jimarez ,  Cynthia S. Milkovich ,  Mark V. Pierson

IPC: H01L021/44

CPC classification number: H01L24/12 ,  B23K1/0016 ,  B23K2101/42 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05671 ,  H01L2224/10126 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/81013 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/351 ,  H05K3/0032 ,  H05K3/3436 ,  H05K2201/0379 ,  H05K2201/10977 ,  H05K2201/10992 ,  H05K2203/0415 ,  H05K2203/043 ,  H05K2203/0465 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2924/00014

Abstract: An electrical structure, and associated method of fabrication, for reducing thermally induced strain in a structure that couples a first conductive body of a first substrate to a second conductive body of a second substrate (e.g., a chip to a chip carrier; a chip carrier to a circuit card). The melting point of the first conductive body exceeds the melting point of the second conductive body. The second conductive body may include eutectic lead-tin alloy, while the first conductive body may include non-eutectic lead-tin alloy. A portion of the first conductive body is coated with, or volumetrically surrounded by, a material that is nonsolderable and nonconductive. The first and second conductive bodies are coupled mechanically and electrically by surface adhesion at an uncoated portion of the first conductive body, by application of a temperature that lies between the melting points of the first and second conductive bodies.

Abstract translation: 一种电结构和相关制造方法，用于减少将第一衬底的第一导体与第二衬底的第二导电体（例如，芯片耦合到芯片载体;芯片载体）的结构中的热诱导应变 到电路卡）。 第一导电体的熔点超过第二导电体的熔点。 第二导电体可以包括共晶铅锡合金，而第一导电体可以包括非共晶铅锡合金。 第一导电体的一部分被不可焊接和不导电的材料涂覆或体积地包围。 通过施加位于第一和第二导电体的熔点之间的温度，第一和第二导电体通过在第一导电体的未涂覆部分处的表面粘附机械和电连接。