Invention Application
US20030178649A1 STRESS REDUCTION IN FLIP-CHIP PBGA PACKAGING BY UTILIZING SEGMENTED CHIP CARRIERS
有权
使用分离式芯片运输的片状PBGA包装中的应力减少
- Patent Title: STRESS REDUCTION IN FLIP-CHIP PBGA PACKAGING BY UTILIZING SEGMENTED CHIP CARRIERS
- Patent Title (中): 使用分离式芯片运输的片状PBGA包装中的应力减少
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Application No.: US10103602Application Date: 2002-03-20
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Publication No.: US20030178649A1Publication Date: 2003-09-25
- Inventor: Krishna Darbha , Miguel A. Jimarez , Matthew M. Reiss , Sanjeev B. Sathe , Charles G. Woychik
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Main IPC: H01L027/10
- IPC: H01L027/10
Abstract:
A method and structure to electrically couple a semiconductor device to a substrate that is divided into a plurality of segments. Alternatively, a semiconductor device may be divided into a plurality of segments and the plurality of segments are electrically coupled to a single substrate.
Public/Granted literature
- US06639302B2 Stress reduction in flip-chip PBGA packaging by utilizing segmented chip carries Public/Granted day:2003-10-28
Information query
