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    Toughness, adhesion and smooth metal lines of porous low k dielectric interconnect structures
    1.
    发明申请
    Toughness, adhesion and smooth metal lines of porous low k dielectric interconnect structures 有权
    多孔低k电介质互连结构的韧性，粘附性和光滑的金属线

    公开(公告)号：US20030114013A1

    公开(公告)日：2003-06-19

    申请号：US10290682

    申请日：2002-11-08

    Applicant: International Business Machines Corporation

    Inventor： Jeffrey C. Hedrick ,  Kang-Wook Lee ,  Kelly Malone ,  Christy S. Tyberg

    IPC: H01L021/302 ,  H01L021/461

    CPC classification number: H01L21/22 ,  H01L21/02118 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02282 ,  H01L21/02362 ,  H01L21/31695 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76835 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  Y10T428/31663 ,  H01L2924/00

    Abstract: A structure useful for electrical interconnection comprises a substrate; a plurality of porous dielectric layers disposed on the substrate; an etch stop layer disposed between a first of the dielectric layers and a second of the dielectric layers; and at least one thin, tough, non-porous dielectric layer disposed between at least one of the porous dielectric layers and the etch stop layer. A method for forming the structure comprising forming a multilayer stack of porous dielectric layers on the substrate, the stack including the plurality of porous dielectric layers, and forming a plurality of patterned metal conductors within the multilayer stack. Curing of the multilayer dielectric stack may be in a single cure step in a furnace. The application and hot plate baking of the individual layers of the multi layer dielectric stack may be accomplished in a single spin-coat tool, without being removed, to fully cure the stack until all dielectric layers have been deposited.

    Abstract translation: 用于电互连的结构包括：基底; 设置在所述基板上的多个多孔介电层; 设置在第一电介质层和第二介电层之间的蚀刻停止层; 以及设置在至少一个多孔电介质层和蚀刻停止层之间的至少一个薄的，韧性的无孔介电层。 一种用于形成所述结构的方法，包括在所述衬底上形成多层介电层的多层堆叠，所述堆叠包括所述多个多孔介电层，以及在所述多层堆叠内形成多个图案化的金属导体。 多层电介质堆叠的固化可以在炉中的单一固化步骤中。 多层电介质堆叠的各层的应用和热板烘烤可以在单个旋涂工具中实现，而不被去除，以完全固化堆叠，直到所有电介质层已经沉积。

    IMPROVED FORMATION OF POROUS INTERCONNECTION LAYERS
    2.
    发明申请
    IMPROVED FORMATION OF POROUS INTERCONNECTION LAYERS 审中-公开
    改进形成多孔互连层

    公开(公告)号：US20040130027A1

    公开(公告)日：2004-07-08

    申请号：US10338105

    申请日：2003-01-07

    Applicant: International Business Machines Corporation

    Inventor： Shyng-Tsong Chen ,  Stephen M. Gates ,  Jeffrey C. Hedrick ,  Kelly Malone ,  Satyanarayana Nitta ,  Christy S. Tyberg

    IPC: H01L023/48 ,  H01L023/52 ,  H01L029/40

    CPC classification number: H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method and structure for forming an integrated circuit structure is disclosed that forms at least one first layer comprising logical and functional devices and forms at least one interconnection layer above the first layer. The interconnection layer is adapted to form electrical connections between the logical and functional devices. The interconnection layer is made by first forming a dielectric layer. The dielectric layer includes a first material and a second material, wherein the second material is less stable at manufacturing environmental conditions (e.g., the processing conditions discussed below) than the first material. The nullsecond materialnull comprises a porogen and the nullfirst materialnull comprises a matrix polymer. The invention then forms conductive features in the dielectric layer and removes (e.g., by heating) the second material from the dielectric layer to create air pockets in the interconnection layer where the second material was positioned.

    Abstract translation: 公开了一种用于形成集成电路结构的方法和结构，其形成包括逻辑和功能器件的至少一个第一层，并且在第一层上方形成至少一个互连层。 互连层适于在逻辑和功能设备之间形成电连接。 互连层通过首先形成介电层制成。 电介质层包括第一材料和第二材料，其中第二材料在制造环境条件（例如，下面讨论的处理条件）下比第一材料更不稳定。 “第二材料”包括致孔剂，“第一材料”包括基质聚合物。 然后，本发明在电介质层中形成导电特征，并且从电介质层移除（例如通过加热）第二材料，以在第二材料定位的互连层中形成气穴。

    Polycarbosilane buried etch stops in interconnect structures
    4.
    发明申请
    Polycarbosilane buried etch stops in interconnect structures 有权
    聚碳硅烷掩埋蚀刻在互连结构中停止

    公开(公告)号：US20040147111A1

    公开(公告)日：2004-07-29

    申请号：US10699238

    申请日：2003-10-31

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Elbert E. Huang ,  Kaushik A. Kumar ,  Kelly Malone ,  Dirk Pfeiffer ,  Muthumanickam Sankarapandian ,  Christy S. Tyberg

    IPC: H01L021/4763

    CPC classification number: H01L21/76801 ,  H01L21/76807 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76835 ,  Y10S438/97

    Abstract: Interconnect structures having buried etch stop layers with low dielectric constants and methods relating to the generation of such buried etch stop layers are described herein. The inventive interconnect structure comprises a buried etch stop layer comprised of a polymeric material having a composition SivNwCxOyHz, where 0.05nullvnull0.8, 0nullwnull0.9, 0.05nullxnull0.8, 0nullynull0.3, 0.05nullznull0.8 for vnullwnullxnullynullznull1; a via level interlayer dielectric that is directly below said buried etch stop layer; a line level interlayer dielectric that is directly above said buried etch stop layer; and conducting metal features that traverse through said via level dielectric, said line level dielectric, and said buried etch stop layer.

    Abstract translation: 本文描述了具有低介电常数的掩埋蚀刻停止层的互连结构和与产生这种掩埋蚀刻停止层有关的方法。 本发明的互连结构包括由具有组成SivNwCxOyHz的聚合物材料组成的掩埋蚀刻停止层，其中0.05 <= v <= 0.8,0 <= w <= 0.9,0.05 <= x <= 0.8,0 <= y < 对于v + w + x + y + z = 1，= 0.3,0.05 <= z <= 0.8; 位于所述掩埋蚀刻停止层正下方的通孔层间电介质; 位于所述掩埋蚀刻停止层正上方的线级层间电介质; 以及导电穿过所述通孔级电介质，所述线级电介质和所述掩埋蚀刻停止层的金属特征。

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