公开(公告)号：US20040207084A1

公开(公告)日：2004-10-21

申请号：US10648884

申请日：2003-08-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jeffrey C. Hedrick ,  Elbert E. Huang

IPC: H01L023/48 ,  H01L021/4763

CPC classification number: H01L21/022 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02205 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/0234 ,  H01L21/3121 ,  H01L21/314 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76844 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Structures having low-k multilayered dielectric diffusion barrier layer having at least one low-k sublayer and at least one air barrier sublayer are described herein. The multilayered dielectric diffusion barrier layer are diffusion barriers to metal and barriers to air permeation. Methods and compositions relating to the generation of the structures are also described. The advantages of utilizing these low-k multilayered dielectric diffusion barrier layer is a gain in chip performance through a reduction in capacitance between conducting metal features and an increase in reliability as the multilayered dielectric diffusion barrier layer are impermeable to air and prevent metal diffusion.

Abstract translation: 本文描述了具有至少一个低k​​子层和至少一个空气阻挡子层的具有低k多层介电扩散阻挡层的结构。 多层电介质扩散阻挡层是对金属的扩散屏障和空气渗透屏障。 还描述了与生成结构有关的方法和组合物。 利用这些低k多层介质扩散阻挡层的优点是通过降低导电金属特性之间的电容并且随着多层电介质扩散阻挡层对空气不透气并防止金属扩散而增加可靠性，可以提高芯片性能。

公开(公告)号：US20040147111A1

公开(公告)日：2004-07-29

申请号：US10699238

申请日：2003-10-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Elbert E. Huang ,  Kaushik A. Kumar ,  Kelly Malone ,  Dirk Pfeiffer ,  Muthumanickam Sankarapandian ,  Christy S. Tyberg

IPC: H01L021/4763

CPC classification number: H01L21/76801 ,  H01L21/76807 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76835 ,  Y10S438/97

Abstract: Interconnect structures having buried etch stop layers with low dielectric constants and methods relating to the generation of such buried etch stop layers are described herein. The inventive interconnect structure comprises a buried etch stop layer comprised of a polymeric material having a composition SivNwCxOyHz, where 0.05nullvnull0.8, 0nullwnull0.9, 0.05nullxnull0.8, 0nullynull0.3, 0.05nullznull0.8 for vnullwnullxnullynullznull1; a via level interlayer dielectric that is directly below said buried etch stop layer; a line level interlayer dielectric that is directly above said buried etch stop layer; and conducting metal features that traverse through said via level dielectric, said line level dielectric, and said buried etch stop layer.

Abstract translation: 本文描述了具有低介电常数的掩埋蚀刻停止层的互连结构和与产生这种掩埋蚀刻停止层有关的方法。 本发明的互连结构包括由具有组成SivNwCxOyHz的聚合物材料组成的掩埋蚀刻停止层，其中0.05 <= v <= 0.8,0 <= w <= 0.9,0.05 <= x <= 0.8,0 <= y < 对于v + w + x + y + z = 1，= 0.3,0.05 <= z <= 0.8; 位于所述掩埋蚀刻停止层正下方的通孔层间电介质; 位于所述掩埋蚀刻停止层正上方的线级层间电介质; 以及导电穿过所述通孔级电介质，所述线级电介质和所述掩埋蚀刻停止层的金属特征。

公开(公告)号：US20040127001A1

公开(公告)日：2004-07-01

申请号：US10331038

申请日：2002-12-27

Applicant: International Business Machines Corporation

Inventor： Matthew E. Colburn ,  Elbert E. Huang ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Katherine L. Saenger

IPC: H01L021/3205

CPC classification number: H01L21/76808 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating low k and ultra-low k multilayer interconnect structures on a substrate includes: a set of interconnects separated laterally by air gaps; forming a support layer in the via level of a dual damascene structure that is only under the metal line; removing a sacrificial dielectric through a perforated bridge layer that connects the top surfaces of the interconnects laterally; performing multilevel extraction of a sacrificial layer; sealing the bridge in a controlled manner; and decreasing the effective dielectric constant of a membrane by perforating it using sub-optical lithography patterning techniques.

Abstract translation: 用于在衬底上制造低k和超低k多层互连结构的方法包括：一组通过气隙横向分离的互连; 在仅在金属线下面的双镶嵌结构的通孔层中形成支撑层; 通过横向连接互连的顶表面的穿孔桥接层去除牺牲电介质; 执行牺牲层的多级提取; 以受控的方式密封桥梁; 并通过使用亚光学光刻图案化技术对膜进行穿孔来降低膜的有效介电常数。