知搜-全球专利检索

  1. 登录
  2. 注册

搜索结果

49 条记录 (耗时 0.026 秒)

    DUAL REDISTRIBUTION LAYER STRUCTURE
    5.
    发明申请
    DUAL REDISTRIBUTION LAYER STRUCTURE 有权

    公开(公告)号：US20210028061A1

    公开(公告)日：2021-01-28

    申请号：US16518166

    申请日：2019-07-22

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Mukta G. Farooq ,  James J. Kelly

    IPC分类号： H01L21/768 ,  H01L25/065 ,  H01L25/00 ,  H01L23/538

    摘要： A method for fabricating a dual redistribution layer (RDL) interposer structure is provided. The method includes etching a semiconductor substrate to expose natural crystallographic planes to form trenches. The method also includes depositing conductive material within the trenches of the etched semiconductor substrate to form vias for an interposer structure. The method includes placing back end of line (BEOL) inter-chip wiring on a top side of the interposer structure using a first RDL. The method includes exposing the vias on a back side of the interposer structure. The method further includes forming power RDLs on a back side of the interposer structure using conductive lines in a dielectric layer.

    VOID-FREE METALLIC INTERCONNECT STRUCTURES WITH SELF-FORMED DIFFUSION BARRIER LAYERS
    6.
    发明申请
    VOID-FREE METALLIC INTERCONNECT STRUCTURES WITH SELF-FORMED DIFFUSION BARRIER LAYERS 审中-公开

    公开(公告)号：US20200020577A1

    公开(公告)日：2020-01-16

    申请号：US16564518

    申请日：2019-09-09

    申请人： International Business Machines Corporation

    发明人： Joseph F. Maniscalco ,  Koichi Motoyama ,  James J. Kelly ,  Hosadurga Shobha ,  Chih-Chao Yang

    IPC分类号： H01L21/768

    摘要： Methods are provided for fabricating void-free metallic interconnect structures with self-formed diffusion barrier layers. A seed layer is deposited to line an etched opening in a dielectric layer. A metallic capping layer is selectively deposited on upper portions and upper sidewall surfaces of the seed layer which define an aperture into the etched opening. An electroplating process is performed to plate metallic material on exposed surfaces of the seed layer within the etched opening, which are not covered by the capping layer to form a metallic interconnect. The capping layer prohibits plating of metallic material on the capping layer and closing the aperture before the electroplating process is complete. A thermal anneal process is performed to cause the metallic material of the metallic capping layer to diffuse though the metallic interconnect and create a self-formed diffusion barrier layer between the metallic interconnect and the surfaces of the etched opening.

    WAFER BACKSIDE PARTICLE MITIGATION
    8.
    发明申请
    WAFER BACKSIDE PARTICLE MITIGATION 有权
    WAFER背面颗粒减轻

    公开(公告)号：US20160049311A1

    公开(公告)日：2016-02-18

    申请号：US14459745

    申请日：2014-08-14

    申请人： International Business Machines Corporation

    发明人： Marc A. Bergendahl ,  James J. Demarest ,  Alex R. Hubbard ,  Richard Johnson ,  Ryan O. Jung ,  James J. Kelly ,  Sanjay C. Mehta ,  Alexander Reznicek ,  Allan W. Upham

    IPC分类号： H01L21/322 ,  H01L21/02 ,  H01L21/3105

    CPC分类号： H01L21/02532 ,  H01L21/0209 ,  H01L21/0274

    摘要： A method of particle mitigation which includes obtaining a semiconductor wafer having a nonfunctional backside and a functional frontside on which semiconductor devices are formed by one or more lithography processes; coating the backside with a layer comprising silicon or amorphous carbon; planarizing the coated backside by a planarizing process; placing the semiconductor wafer onto a wafer chuck such that the wafer chuck makes direct contact with the coated backside; and while maintaining the coated backside in direct contact with the wafer chuck, performing a first lithographic process on the frontside.

    摘要翻译： 一种减少粒子的方法，其包括获得具有非功能背面的半导体晶片和通过一个或多个光刻工艺形成半导体器件的功能前沿; 用包含硅或无定形碳的层涂覆背面; 通过平坦化工艺平整涂覆的背面; 将半导体晶片放置在晶片卡盘上，使得晶片卡盘与涂覆的背面直接接触; 并且在将涂覆的背面保持与晶片卡盘直接接触的同时，在前侧执行第一光刻处理。

    Superfilled metal contact vias for semiconductor devices
    9.
    发明授权
    Superfilled metal contact vias for semiconductor devices 有权
    用于半导体器件的超填充金属接触孔

    公开(公告)号：US08698318B2

    公开(公告)日：2014-04-15

    申请号：US13760373

    申请日：2013-02-06

    申请人： International Business Machines Corporation

    发明人： James J. Kelly ,  Veeraraghavan S. Basker ,  Balasubramanian Pranatharthi Haran ,  Soon-Cheon Seo ,  Tuan A. Vo

    IPC分类号： H01L29/40

    CPC分类号： H01L21/2885 ,  H01L21/76843 ,  H01L21/76873 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In accordance with one aspect of the invention, a method is provided for fabricating a semiconductor element having a contact via. In such method, a hole can be formed in a dielectric layer to at least partially expose a region including at least one of semiconductor or conductive material. A seed layer can be deposited over a major surface of the dielectric layer and over a surface within the hole. In one embodiment, the seed layer can include a metal selected from the group consisting of iridium, osmium, palladium, platinum, rhodium, and ruthenium. A layer consisting essentially of cobalt can be electroplated over the seed layer within the hole to form a contact via in electrically conductive communication with the region.

    摘要翻译： 根据本发明的一个方面，提供了一种用于制造具有接触通孔的半导体元件的方法。 在这种方法中，可以在电介质层中形成孔以至少部分地暴露包括半导体或导电材料中的至少一种的区域。 种子层可以沉积在电介质层的主表面上并且在孔内的表面上。 在一个实施方案中，种子层可以包括选自铱，锇，钯，铂，铑和钌的金属。 基本上由钴组成的层可以电镀在孔内的种子层上，以形成与该区域导电连通的接触通孔。