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公开(公告)号：US10698432B2
公开(公告)日：2020-06-30
申请号：US13801777
申请日：2013-03-13
Applicant: Intel Corporation
Inventor： Yi-Chun Shih , Kaushik Mazumdar , Stephen T. Kim , Rinkle Jain , James W. Tschanz , Muhammad M. Khellah
Abstract: Described is an apparatus which comprises: a plurality of transistors coupled to an input power supply and to a load; a first comparator with a first node coupled to the load, and a second node coupled to a first reference; a second comparator with a first node coupled to the load, and a second node coupled to a second reference, the second reference being different from the first reference; and a logic unit to receive output of the first comparator and output of the second comparator, the logic unit to turn on or off transistors of the plurality of transistors according to outputs of the first and second comparators.
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公开(公告)号：US09916884B2
公开(公告)日：2018-03-13
申请号：US15115461
申请日：2014-03-07
Applicant: Intel Corporation
Inventor： Charles Augustine , Carlos Tokunaga , James W. Tschanz
CPC classification number: G11C11/1695 , G06F21/34 , G06F21/73 , G06F21/79 , G09C1/00 , G11C7/16 , G11C7/24 , G11C11/16 , G11C11/1659 , G11C11/1673 , G11C13/0002 , G11C13/0004 , G11C13/004 , G11C13/0059 , G11C2013/0045 , G11C2013/005 , H03M1/12 , H03M1/124 , H04L9/0866
Abstract: Described is a physically unclonable functional circuit comprising: a resistive memory device (e.g., an MTJ device) having at least two terminals; a transistor coupled to one of the at least two terminals of the resistive memory device; and an analog-to-digital converter (ADC) having an input coupled to the one of the at least two terminals of the resistive memory device.
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公开(公告)号：US09722606B2
公开(公告)日：2017-08-01
申请号：US15331280
申请日：2016-10-21
Applicant: INTEL CORPORATION
Inventor： Arijit Raychowdhury , Charles Augustine , James W. Tschanz , Vivek K. De
CPC classification number: H03K19/0016 , G05F1/10 , G05F1/461 , G05F1/59 , G06F1/3287 , G06F1/3296 , H03K3/0377 , H03K19/0008
Abstract: Described is an apparatus which comprises: a clamp coupled between a first power supply and a second power supply, the clamp including a plurality of transistors, a circuit to operate with the second power supply; and a control unit to turn on and off the plurality of transistors to adjust the second power supply when the apparatus enters a low power mode. The control unit includes a first comparator to compare the second power supply with a first reference, a second comparator to compare the second power supply with a second reference, and a counter. The counter counts up when the second power supply is higher than the first reference and counts down when the second power supply is lower than the second reference.
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公开(公告)号：US09514796B1
公开(公告)日：2016-12-06
申请号：US14751801
申请日：2015-06-26
Applicant: Intel Corporation
Inventor： Charles Augustine , Shigeki Tomishima , Wei Wu , Shih-Lien Lu , James W. Tschanz , Georgios Panagopoulos , Helia Naeimi
CPC classification number: G11C11/1675 , G11C11/1659 , G11C11/1677 , G11C11/1693 , G11C11/1697
Abstract: An apparatus is described that includes a semiconductor chip memory array having resistive storage cells. The apparatus also includes a comparator to compare a first word to be written into the array against a second word stored in the array at the location targeted by a write operation that will write the first word into the array. The apparatus also includes circuitry to iteratively write to one or more bit locations where a difference exists between the first word and the second word with increasing write current intensity with each successive iteration.
Abstract translation: 描述了一种包括具有电阻存储单元的半导体芯片存储器阵列的装置。 该装置还包括比较器，用于将写入阵列的第一个字与存储在阵列中的第二个字进行比较，该第二个字由写入操作所指向的位置将第一个字写入数组。 该装置还包括用于迭代地写入一个或多个比特位置的电路，其中在每个连续的迭代中随着写入电流强度的增加而在第一个字和第二个字之间存在差异。
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公开(公告)号：US09369277B2
公开(公告)日：2016-06-14
申请号：US14325844
申请日：2014-07-08
Applicant: INTEL CORPORATION
Inventor： Charles Augustine , Carlos Tokunaga , James W. Tschanz
CPC classification number: H04L9/0877 , G09C1/00 , H04L9/0816 , H04L9/0866 , H04L9/3278 , H04L2209/12 , H04L2209/24
Abstract: Embodiments include apparatuses, methods, and systems for generation of an encryption key. In various embodiments, an authentication circuit may include a first bank of spin-torque nano-oscillators (STNOs) including a plurality of STNOs to generate respective oscillation signals and a second bank of STNOs including a plurality of STNOs to generate respective oscillation signals. The authentication circuit may further include a key generation circuit to select a first oscillation signal from the plurality of oscillation signals associated with the first bank of STNOs and a second oscillation signal from the plurality of oscillation signals associated with the second bank of STNOs. The key generation circuit may generate an encryption key based on a frequency of the first oscillation signal and a frequency of the second oscillation signal.
Abstract translation: 实施例包括用于生成加密密钥的装置，方法和系统。 在各种实施例中，认证电路可以包括包括多个STNO的第一组自旋扭矩纳秒振荡器（STNO）以产生各个振荡信号，以及包括多个STNO的第二组STNO以产生相应的振荡信号。 认证电路还可以包括密钥生成电路，用于从与第一组STNO相关联的多个振荡信号中选择第一振荡信号，以及从与第二组STNO相关联的多个振荡信号中选择第二振荡信号。 密钥生成电路可以基于第一振荡信号的频率和第二振荡信号的频率生成加密密钥。
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Patent Agency Ranking
公开(公告)号：US20160034338A1
公开(公告)日：2016-02-04
申请号：US14878985
申请日：2015-10-08
Applicant: INTEL CORPORATION
Inventor： Keith A. Bowman , James W. Tschanz , Nam Sung Kim , Janice C. Lee , Christopher B. Wilkerson , Shih-Lien L. Lu , Tanay Karnik , Vivek K. De
IPC: G06F11/07
CPC classification number: G01R31/3177 , G01R31/31723 , G01R31/31725 , G01R31/31727 , G06F1/10 , G06F11/0706 , G06F11/0757 , G06F11/0793 , H03K3/0375
Abstract: Sequential circuits with error-detection are provided. They may, for example, be used to replace traditional master-slave flip-flops, e.g., in critical path circuits to detect and initiate correction of late transitions at the input of the sequential. In some embodiments, such sequentials may comprise a transition detector with a time borrowing latch.
Abstract translation: 提供了具有错误检测的顺序电路。 例如，它们可以用于替代传统的主从触发器，例如在关键路径电路中，以检测并启动在顺序输入处的后期转换的校正。 在一些实施例中，这样的顺序可以包括具有时间借用锁存器的转换检测器。
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公开(公告)号：US10600462B2
公开(公告)日：2020-03-24
申请号：US15495936
申请日：2017-04-24
Applicant: INTEL CORPORATION
Inventor： Charles Augustine , Shigeki Tomishima , James W. Tschanz , Shih-Lien L. Lu
Abstract: In accordance with various embodiments of this disclosure, stray magnetic field mitigation in an MRAM memory such as a spin transfer torque (STT) random access memory (RAM), STTRAM is described. In one embodiment, retention of bitcell bit value storage states in an STTRAM may be facilitated by generating magnetic fields to compensate for stray magnetic fields which may cause bitcells of the memory to change state. In another embodiment, retention of bitcell bit value storage states in an STTRAM may be facilitated by selectively suspending access to a row of memory to temporarily terminate stray magnetic fields which may cause bitcells of the memory to change state. Other aspects are described herein.
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公开(公告)号：US09948179B2
公开(公告)日：2018-04-17
申请号：US15032981
申请日：2013-12-20
Applicant: Intel Corporation
Inventor： Jaydeep P. Kulkarni , Pascal A. Meinerzhagen , Dinesh Somasekhar , James W. Tschanz , Vivek K. De
CPC classification number: H02M3/073 , G06F3/041 , H02J7/00 , H03K3/0377 , H03K19/21
Abstract: Described is an apparatus for power management. The apparatus comprises: a first power supply node; a second power supply node; a controllable device coupled to the first power supply node and to the second power supply node, the controllable device operable to short the first power supply node to the second power supply node; a load coupled to the second power supply node; and a charge recovery pump (CRP) coupled to the first and second power supply nodes.
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公开(公告)号：US09870012B2
公开(公告)日：2018-01-16
申请号：US13976223
申请日：2012-09-25
Applicant: Intel Corporation
Inventor： Arijit Raychowdhury , Dinesh Somasekhar , James W. Tschanz , Vivek K. De
CPC classification number: G05F1/577 , G05F1/468 , G05F1/56 , G06F1/06 , G06F1/26 , H03L7/085 , Y10T307/406
Abstract: Described is an apparatus which comprises: a first oscillator to generate a first clock signal a second oscillator to generate a second clock signal; a phase frequency detector to detect phase difference between the first and second clock signals, and to generate a phase difference; and an output stage, coupled to a load, to generate a power supply for the load according to the phase difference.
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公开(公告)号：US20170322617A1
公开(公告)日：2017-11-09
申请号：US15409366
申请日：2017-01-18
Applicant: Intel Corporation
Inventor： Subramaniam Maiyuran , Muhammad M. Khellah , James W. Tschanz
IPC: G06F1/32
CPC classification number: G06F1/3296 , G06F1/324 , G06F1/3243 , G06F1/3287 , Y02D10/126 , Y02D10/152 , Y02D10/171 , Y02D10/172
Abstract: Voltage regulation of processor sub-domains supplied by a same voltage domain power supply rail. Voltage to certain logic units within the voltage domain may be reduced relative to other logic units of the voltage domain, reducing idle time at high power. In an embodiment, a first voltage-regulated sub-domain includes at least one execution unit (EU) while a second voltage-regulated sub-domain includes at least one texture sampler to provide flexibility in setting the graphics core power-performance point beyond modulating active EU count through power domain (gating) control. In embodiments, a sub-domain voltage is regulated by an on-chip DLDO for fast voltage switching. Clock frequency and sub-domain voltage may be switched faster than the voltage of the voltage domain supply rail, permitting a more finely grained power management that can be responsive to EU workload demand.
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