公开(公告)号：US20240162141A1

公开(公告)日：2024-05-16

申请号：US18419015

申请日：2024-01-22

申请人： Intel Corporation

发明人： Ehren MANNEBACH ,  Aaron LILAK ,  Hui Jae YOO ,  Patrick MORROW ,  Anh PHAN ,  Willy RACHMADY ,  Cheng-Ying HUANG ,  Gilbert DEWEY ,  Rishabh MEHANDRU

IPC分类号： H01L23/522 ,  H01L21/8234 ,  H01L25/16 ,  H01L29/06

CPC分类号： H01L23/5226 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823475 ,  H01L21/823481 ,  H01L25/16 ,  H01L29/0653

摘要： Embodiments disclosed herein include electronic systems with vias that include a horizontal and vertical portion in order to provide interconnects to stacked components, and methods of forming such systems. In an embodiment, an electronic system comprises a board, a package substrate electrically coupled to the board, and a die electrically coupled to the package substrate. In an embodiment the die comprises a stack of components, and a via adjacent to the stack of components, wherein the via comprises a vertical portion and a horizontal portion.

公开(公告)号：US20230369399A1

公开(公告)日：2023-11-16

申请号：US18225440

申请日：2023-07-24

申请人： Intel Corporation

发明人： Ehren MANNEBACH ,  Anh PHAN ,  Aaron LILAK ,  Willy RACHMADY ,  Gilbert DEWEY ,  Cheng-Ying HUANG ,  Richard SCHENKER ,  Hui Jae YOO ,  Patrick MORROW

IPC分类号： H01L29/06 ,  H01L27/088 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423

CPC分类号： H01L29/068 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

摘要： Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using multiple bottom-up oxidation approaches, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires. All nanowires of the vertical arrangement of nanowires are oxide nanowires. A gate stack is over the vertical arrangement of nanowires, around each of the oxide nanowires. The gate stack includes a conductive gate electrode.

公开(公告)号：US20220199807A1

公开(公告)日：2022-06-23

申请号：US17129867

申请日：2020-12-21

申请人： Intel Corporation

发明人： Noriyuki SATO ,  Sarah ATANASOV ,  Abhishek A. Sharma ,  Bernhard SELL ,  Chieh-Jen KU ,  Elliot N. TAN ,  Hui Jae YOO ,  Travis W. LAJOIE ,  Van H. LE ,  Pei-Hua WANG ,  Jason PECK ,  Tobias BROWN-HEFT

IPC分类号： H01L29/66 ,  H01L27/092 ,  H01L21/8234

摘要： Thin film transistors fabricated using a spacer as a fin are described. In an example, a method of forming a fin transistor structure includes patterning a plurality of backbone pillars on a semiconductor substrate. The method may then include conformally depositing a spacer layer over the plurality of backbone pillars and the semiconductor substrate. A spacer etch of the spacer layer is then performed to leave a sidewall of the spacer layer on a backbone pillar to form a fin of the fin transistor structure. Other embodiments may be described and claimed

公开(公告)号：US20210057413A1

公开(公告)日：2021-02-25

申请号：US16954126

申请日：2018-03-28

申请人： Gilbert DEWEY ,  Ravi PILLARISETTY ,  Jack T. KAVALIEROS ,  Aaron D. LILAK ,  Willy RACHMADY ,  Rishabh MEHANDRU ,  Kimin JUN ,  Anh PHAN ,  Hui Jae YOO ,  Patrick MORROW ,  Cheng-Ying HUANG ,  Matthew V. METZ ,  Intel Corporation

发明人： Gilbert DEWEY ,  Ravi PILLARISETTY ,  Jack T. KAVALIEROS ,  Aaron D. LILAK ,  Willy RACHMADY ,  Rishabh MEHANDRU ,  Kimin JUN ,  Anh PHAN ,  Hui Jae YOO ,  Patrick MORROW ,  Cheng-Ying HUANG ,  Matthew V. METZ

IPC分类号： H01L27/092 ,  H01L21/822 ,  H01L29/08 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/06 ,  H01L29/66 ,  H01L29/06

摘要： An integrated circuit structure comprises a lower device layer that includes a first structure comprising a plurality of PMOS transistors. An upper device layer is formed on the lower device layer, wherein the upper device layer includes a second structure comprising a plurality of NMOS transistors having a group III-V material source/drain region.

公开(公告)号：US20200303238A1

公开(公告)日：2020-09-24

申请号：US16358520

申请日：2019-03-19

申请人： Intel Corporation

发明人： Ehren MANNEBACH ,  Aaron LILAK ,  Rishabh MEHANDRU ,  Hui Jae YOO ,  Patrick MORROW ,  Kevin LIN

IPC分类号： H01L21/768 ,  H01L29/417 ,  H01L21/762 ,  H01L21/683 ,  H01L23/31

摘要： Embodiments herein describe techniques for a semiconductor device including a carrier wafer, and an integrated circuit (IC) formed on a device wafer bonded to the carrier wafer. The IC includes a front end layer having one or more transistors at front end of the device wafer, and a back end layer having a metal interconnect coupled to the one or more transistors. One or more gaps may be formed by removing components of the one or more transistors. Furthermore, the IC includes a capping layer at backside of the device wafer next to the front end layer of the device wafer, filling at least partially the one or more gaps of the front end layer. Moreover, the IC includes one or more air gaps formed within the one or more gaps, and between the capping layer and the back end layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20200006388A1

公开(公告)日：2020-01-02

申请号：US16024696

申请日：2018-06-29

申请人： Intel Corporation

发明人： Gilbert DEWEY ,  Patrick MORROW ,  Aaron LILAK ,  Willy RACHMADY ,  Anh PHAN ,  Ehren MANNEBACH ,  Hui Jae YOO ,  Abhishek SHARMA ,  Van H. LE ,  Cheng-Ying HUANG

IPC分类号： H01L27/12 ,  H01L29/786 ,  H01L29/78 ,  H01L21/8258

摘要： Embodiments herein describe techniques for an integrated circuit (IC). The IC may include a first transistor, an insulator layer above the first transistor, and a second transistor above the insulator layer. The first transistor may be a p-type transistor including a channel in a substrate, a first source electrode, and a first drain electrode. A first metal contact may be coupled to the first source electrode, while a second metal contact may be coupled to the first drain electrode. The insulator layer may be next to the first metal contact, and next to the second metal contact. The second transistor may include a second source electrode, and a second drain electrode. The second source electrode may be coupled to the first metal contact, or the second drain electrode may be coupled to the second metal contact. Other embodiments may be described and/or claimed.

公开(公告)号：US20190035677A1

公开(公告)日：2019-01-31

申请号：US16070172

申请日：2016-03-30

申请人： Intel Corporation

发明人： Manish CHANDHOK ,  Richard E. SCHENKER ,  Hui Jae YOO ,  Kevin L. LIN ,  Jasmeet S. CHAWLA ,  Stephanie A. BOJARSKI ,  Satyarth SURI ,  Colin T. CARVER ,  Sudipto NASKAR

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L21/311

CPC分类号： H01L21/76802 ,  H01L21/0337 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76843 ,  H01L21/76847 ,  H01L21/76865 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76889 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53271

摘要： A plurality of interconnect features are formed in an interconnect layer on a first insulating layer on a substrate. An opening in the first insulating layer is formed through at least one of the interconnect features. A gap fill layer is deposited in the opening.

公开(公告)号：US20240234422A1

公开(公告)日：2024-07-11

申请号：US18614290

申请日：2024-03-22

申请人： Intel Corporation

发明人： Cheng-Ying HUANG ,  Gilbert DEWEY ,  Anh PHAN ,  Nicole K. THOMAS ,  Urusa ALAAN ,  Seung Hoon SUNG ,  Christopher M. NEUMANN ,  Willy RACHMADY ,  Patrick MORROW ,  Hui Jae YOO ,  Richard E. SCHENKER ,  Marko RADOSAVLJEVIC ,  Jack T. KAVALIEROS ,  Ehren MANNEBACH

IPC分类号： H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H10B12/00

CPC分类号： H01L27/0924 ,  H01L29/0673 ,  H01L29/4232 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/7853 ,  H10B12/056

摘要： Embodiments disclosed herein include stacked forksheet transistor devices, and methods of fabricating stacked forksheet transistor devices. In an example, an integrated circuit structure includes a backbone. A first transistor device includes a first vertical stack of semiconductor channels adjacent to an edge of the backbone. A second transistor device includes a second vertical stack of semiconductor channels adjacent to the edge of the backbone. The second transistor device is stacked on the first transistor device.

公开(公告)号：US20240145557A1

公开(公告)日：2024-05-02

申请号：US18408346

申请日：2024-01-09

申请人： Intel Corporation

发明人： Ehren MANNEBACH ,  Aaron LILAK ,  Hui Jae YOO ,  Patrick MORROW ,  Anh PHAN ,  Willy RACHMADY ,  Cheng-Ying HUANG ,  Gilbert DEWEY

IPC分类号： H01L29/417

CPC分类号： H01L29/41741 ,  H01L29/41775

摘要： A device is disclosed. The device includes a first epitaxial region, a second epitaxial region, a first gate region between the first epitaxial region and a second epitaxial region, a first dielectric structure underneath the first epitaxial region, a second dielectric structure underneath the second epitaxial region, a third epitaxial region underneath the first epitaxial region, a fourth epitaxial region underneath the second epitaxial region, and a second gate region between the third epitaxial region and a fourth epitaxial region and below the first gate region. The device also includes, a conductor via extending from the first epitaxial region, through the first dielectric structure and the third epitaxial region, the conductor via narrower at an end of the conductor via that contacts the first epitaxial region than at an opposite end.

公开(公告)号：US20230130273A1

公开(公告)日：2023-04-27

申请号：US18088474

申请日：2022-12-23

申请人： Intel Corporation

发明人： Hui Jae YOO ,  Tejaswi K. INDUKURI ,  Ramanan V. CHEBIAM ,  James S. CLARKE

IPC分类号： H01L21/768 ,  H01L23/532

摘要： A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity ρ1 and the core material exhibits a second resistivity ρ2 and ρ2 is less than ρ1.