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    Integration of a Schottky diode with a MOSFET
    2.
    发明授权
    Integration of a Schottky diode with a MOSFET 有权

    公开(公告)号：US11114557B2

    公开(公告)日：2021-09-07

    申请号：US16647186

    申请日：2018-09-14

    申请人： II-VI Delaware, Inc.

    发明人： Nicolas Thierry-Jebali ,  Hossein Elahipanah ,  Adolf Schöner ,  Sergey Reshanov

    IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/47

    摘要： There is disclosed the integration of a Schottky diode with a MOSFET, more in detail there is a free-wheeling Schottky diode and a power MOSFET on top of a buried grid material structure. Advantages of the specific design allow the whole surface area to be used for MOSFET and Schottky diode structures, the shared drift layer is not limited by Schottky diode or MOSFET design rules and therefore, one can decrease the thickness and increase the doping concentration of the drift layer closer to a punch through design compared to the state of the art. This results in higher conductivity and lower on-resistance of the device with no influence on the voltage blocking performance. The integrated device can operate at higher frequency. The risk for bipolar degradation is avoided.

    Buried Grid Double Junction Barrier Schottky Diode and Method of Making
    3.
    发明公开
    Buried Grid Double Junction Barrier Schottky Diode and Method of Making 审中-公开

    公开(公告)号：US20240355938A1

    公开(公告)日：2024-10-24

    申请号：US18303617

    申请日：2023-04-20

    申请人： II-VI Delaware, Inc.

    发明人： Shuoben Hou ,  Sergey Reshanov ,  Adolf Schöner

    IPC分类号： H01L29/872 ,  H01L29/417 ,  H01L29/66

    CPC分类号： H01L29/872 ,  H01L29/417 ,  H01L29/6606 ,  H01L29/66143 ,  H01L29/47

    摘要： A buried grid double junction barrier Schottky diode may include a drift layer, a grid layer comprising a plurality of grid segments at least partially in the drift layer, a regrown layer on the grid layer and the drift layer, and first and second Schottky material layers. The grid segments may define at least one grid spacing area between adjacent grid segments. The first Schottky material layer may be at least partially on the regrown layer and may at least partially overlap the grid segments of the grid layer. The second Schottky material layer may be at least partially on the regrown layer and may at least partially overlap the grid spacing area(s). The second Schottky material layer may have a different Schottky barrier height than the first Schottky material layer. A method of making a buried grid double junction barrier Schottky diode is also disclosed.

    Feeder design with high current capability
    4.
    发明授权
    Feeder design with high current capability 有权

    公开(公告)号：US11575007B2

    公开(公告)日：2023-02-07

    申请号：US17448790

    申请日：2021-09-24

    申请人： II-VI Delaware, Inc

    发明人： Hossein Elahipanah ,  Nicolas Thierry-Jebali ,  Adolf Schöner ,  Sergey Reshanov

    IPC分类号： H01L29/06 ,  H01L29/16 ,  H01L29/66 ,  H01L29/868

    摘要： A feeder design is manufactured as a structure in a SIC semiconductor material comprising at least two p-type grids in an n-type SiC material (3), comprising at least one epitaxially grown p-type region, wherein an Ohmic contact is applied on the at least one epitaxially grown p-type region, wherein an epitaxially grown n-type layer is applied on at least a part of the at least two p-type grids and the n-type SiC material (3) wherein the at least two p-type grids (4, 5) are applied in at least a first and a second regions at least close to the at least first and second corners respectively and that there is a region in the n-type SiC material (3) between the first and a second regions without any grids.

    Method for manufacturing a grid
    5.
    发明授权
    Method for manufacturing a grid 有权

    公开(公告)号：US11342423B2

    公开(公告)日：2022-05-24

    申请号：US16647094

    申请日：2018-09-14

    申请人： II-VI Delaware, Inc

    发明人： Adolf Schöner ,  Sergey Reshanov ,  Nicolas Thierry-Jebali ,  Hossein Elahipanah

    IPC分类号： H01L21/00 ,  H01L29/40 ,  H01L21/02 ,  H01L21/265 ,  H01L21/285 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/324

    摘要： A grid is manufactured with a combination of ion implant and epitaxy growth. The grid structure is made in a SiC semiconductor material with the steps of a) providing a substrate comprising a doped semiconductor SiC material, said substrate comprising a first layer (n1), b) by epitaxial growth adding at least one doped semiconductor SiC material to form separated second regions (p2) on the first layer (n1), if necessary with aid of removing parts of the added semiconductor material to form separated second regions (p2) on the first layer (n1), and c) by ion implantation at least once at a stage selected from the group consisting of directly after step a), and directly after step b); implanting ions in the first layer (n1) to form first regions (p1). It is possible to manufacture a grid with rounded corners as well as an upper part with a high doping level. It is possible to manufacture a component with efficient voltage blocking, high current conduction, low total resistance, high surge current capability, and fast switching.

    MOSFET in SiC with self-aligned lateral MOS channel
    8.
    发明授权
    MOSFET in SiC with self-aligned lateral MOS channel 有权

    公开(公告)号：US11923450B2

    公开(公告)日：2024-03-05

    申请号：US17817384

    申请日：2022-08-04

    申请人： II-VI Delaware, Inc.

    发明人： Adolf Schoner ,  Sergey Reshanov ,  Nicolas Thierry-Jebali ,  Hossein Elahipanah

    IPC分类号： H01L29/78 ,  H01L21/04 ,  H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L29/66

    CPC分类号： H01L29/7805 ,  H01L21/0465 ,  H01L29/063 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068

    摘要： There is disclosed a method for manufacturing a MOSFET with lateral channel in SiC, said MOSFET comprising simultaneously formed n type regions comprising an access region and a JFET region defining the length of the MOS channel, and wherein the access region and the JFET region are formed by ion implantation by using one masking step. The design is self-aligning so that the length of the MOS channel is defined by simultaneous creating n-type regions on both sides of the channel using one masking step. Any misalignment in the mask is moved to other less critical positions in the device. The risk of punch-through is decreased compared to the prior art. The current distribution becomes more homogenous. The short-circuit capability increases. There is lower Drain-Source specific on-resistance due to a reduced MOS channel resistance. There is a lower JFET resistance due to the possibility to increase the JFET region doping concentration.

    FEEDER DESIGN WITH HIGH CURRENT CAPABILITY
    10.
    发明申请
    FEEDER DESIGN WITH HIGH CURRENT CAPABILITY 有权

    公开(公告)号：US20220020850A1

    公开(公告)日：2022-01-20

    申请号：US17448790

    申请日：2021-09-24

    申请人： II-VI Delaware, Inc

    发明人： Hossein Elahipanah ,  Nicolas Thierry-Jebali ,  Adolf Schöner ,  Sergey Reshanov

    IPC分类号： H01L29/06 ,  H01L29/16 ,  H01L29/66 ,  H01L29/868

    摘要： A feeder design is manufactured as a structure in a SIC semiconductor material comprising at least two p-type grids in an n-type SiC material (3), comprising at least one epitaxially grown p-type region, wherein an Ohmic contact is applied on the at least one epitaxially grown p-type region, wherein an epitaxially grown n-type layer is applied on at least a part of the at least two p-type grids and the n-type SiC material (3) wherein the at least two p-type grids (4, 5) are applied in at least a first and a second regions at least close to the at least first and second corners respectively and that there is a region in the n-type SiC material (3) between the first and a second regions without any grids.