公开(公告)号：US06939751B2

公开(公告)日：2005-09-06

申请号：US10605726

申请日：2003-10-22

申请人： Huilong Zhu ,  Bruce B. Doris ,  Werner A. Rausch ,  Ying Zhang

发明人： Huilong Zhu ,  Bruce B. Doris ,  Werner A. Rausch ,  Ying Zhang

IPC分类号： H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786

CPC分类号： H01L29/66621 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66772 ,  H01L29/7842 ,  H01L29/78687

摘要： An RSD FET device with a recessed channel is formed with a raised silicon sources and drains and a gate electrode structure formed on an SOI structure (a Si layer formed on a substrate) by the steps as follows. Form a SiGe layer over the Si layer and a RSD layer over the SiGe. Etch through the RSD layer and the SiGe to form a gate electrode space reaching down the Si layer. Form a pair of RSD regions separated by the gate electrode space. Line the walls of the gate electrode space with an internal etch stop layer and an inner sidewall spacers. Form a gate electrode inside the inner sidewall spacers on the Si layer. Form external sidewall spacers adjacent to the gate electrode between the RSD regions next to the inner sidewall spacers, and dope the RSD regions, whereby a recessed channel is formed in the SOI silicon layer between the raised source/drain regions thereabove and below the level of the SiGe layer.

摘要翻译： 具有凹陷沟道的RSD FET器件通过以下步骤形成有凸起的硅源和漏极以及形成在SOI结构（形成在衬底上的Si层）上的栅电极结构。 在Si层上形成SiGe层，在SiGe上形成RSD层。 通过RSD层和SiGe蚀刻以形成向下延伸到Si层的栅电极空间。 形成一对被栅电极间隔开的RSD区域。 用内部蚀刻停止层和内侧壁间隔物来排列栅电极空间的壁。 在Si层上的内侧墙壁内部形成栅电极。 在靠近内侧壁间隔物的RSD区域之间形成与栅电极相邻的外侧壁间隔物，并且掺杂RSD区域，由此在SOI硅层之间形成凹陷沟道，在SOI硅层之间的上升源极/漏极区域之间并且低于 SiGe层。

公开(公告)号：US07923782B2

公开(公告)日：2011-04-12

申请号：US10708378

申请日：2004-02-27

申请人： Huilong Zhu ,  Philip J. Oldiges ,  Bruce B. Doris ,  Xinlin Wang ,  Oleg Gluschenkov ,  Huajie Chen ,  Ying Zhang

发明人： Huilong Zhu ,  Philip J. Oldiges ,  Bruce B. Doris ,  Xinlin Wang ,  Oleg Gluschenkov ,  Huajie Chen ,  Ying Zhang

IPC分类号： H01L27/01 ,  H01L27/12

CPC分类号： H01L29/7849 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/7842 ,  H01L29/78603 ,  H01L29/78612 ,  H01L29/78618 ,  H01L29/78687

摘要： Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects.

摘要翻译： 场效应晶体管中的沟道深度由包括在半导体材料的层或衬底内形成的不连续膜或层的层内结构限制。 因此，可以以SOI或UT-SOI技术的方式控制通道深度，但是具有较便宜的衬底和更大的通道深度控制的灵活性，同时避免SOI技术的浮体效应特性。 不连续膜的轮廓或横截面形状可以被控制为奥格或阶梯形状，以改善短通道效应，并且在不增加电容的情况下降低源极/漏极和延伸电阻。 也可以选择用于不连续膜的材料以在衬底或层内从晶体管沟道施加应力，并提供增加的这种应力水平以增加载流子迁移率。 携带者的流动性可能会与其他有利的影响相结合。

公开(公告)号：US07388257B2

公开(公告)日：2008-06-17

申请号：US10711200

申请日：2004-09-01

申请人： Bruce B. Doris ,  Oleg Gluschenkov ,  Ying Zhang ,  Huilong Zhu

发明人： Bruce B. Doris ,  Oleg Gluschenkov ,  Ying Zhang ,  Huilong Zhu

IPC分类号： H01L27/01

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： A multi-gate device has a high-k dielectric layer for a top channel of the gate and a protective layer for use in a finFET device. The high-k dielectric layer is placed on the top surface of the channel of the finFET and may reduce or eliminate silicon consumption in the channel. The use of the high-k dielectric layer on the top surface reduces hysteresis and mobility degradation associated with high-k dielectrics. The protection layer may protect the high-k dielectric layer during an etching process.

摘要翻译： 多栅极器件具有用于栅极顶部沟道的高k电介质层和用于finFET器件的保护层。 高k电介质层被放置在finFET的沟道的顶表面上，并且可以减少或消除沟道中的硅消耗。 在顶表面上使用高k电介质层减少了与高k电介质相关的滞后和迁移率降低。 保护层可以在蚀刻过程中保护高k电介质层。

公开(公告)号：US07767503B2

公开(公告)日：2010-08-03

申请号：US12132853

申请日：2008-06-04

申请人： Huilong Zhu ,  Philip J. Oldiges ,  Bruce B. Doris ,  Xinlin Wang ,  Oleg Gluschenkov ,  Huajie Chen ,  Ying Zhang

发明人： Huilong Zhu ,  Philip J. Oldiges ,  Bruce B. Doris ,  Xinlin Wang ,  Oleg Gluschenkov ,  Huajie Chen ,  Ying Zhang

IPC分类号： H01L21/84 ,  H01L21/336

CPC分类号： H01L29/7849 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/7842 ,  H01L29/78603 ,  H01L29/78612 ,  H01L29/78618 ,  H01L29/78687

摘要： Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects.

摘要翻译： 场效应晶体管中的沟道深度由包括在半导体材料的层或衬底内形成的不连续膜或层的层内结构限制。 因此，可以以SOI或UT-SOI技术的方式控制通道深度，但是具有较便宜的衬底和更大的通道深度控制的灵活性，同时避免SOI技术的浮体效应特性。 不连续膜的轮廓或横截面形状可以被控制为奥格或阶梯形状，以改善短通道效应，并且在不增加电容的情况下降低源极/漏极和延伸电阻。 也可以选择用于不连续膜的材料以在衬底或层内从晶体管沟道施加应力，并提供增加的这种应力水平以增加载流子迁移率。 携带者的流动性可能会与其他有利的影响相结合。

公开(公告)号：US20080242069A1

公开(公告)日：2008-10-02

申请号：US12132853

申请日：2008-06-04

申请人： Huilong Zhu ,  Philip J. Oldiges ,  Bruce B. Doris ,  Xinlin Wang ,  Oleg Gluschenkov ,  Huajie Chen ,  Ying Zhang

发明人： Huilong Zhu ,  Philip J. Oldiges ,  Bruce B. Doris ,  Xinlin Wang ,  Oleg Gluschenkov ,  Huajie Chen ,  Ying Zhang

IPC分类号： H01L21/3205

CPC分类号： H01L29/7849 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/7842 ,  H01L29/78603 ,  H01L29/78612 ,  H01L29/78618 ,  H01L29/78687

摘要： Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects.

摘要翻译： 场效应晶体管中的沟道深度由包括在半导体材料的层或衬底内形成的不连续膜或层的层内结构限制。 因此，可以以SOI或UT-SOI技术的方式控制通道深度，但是具有较便宜的衬底和更大的通道深度控制的灵活性，同时避免SOI技术的浮体效应特性。 不连续膜的轮廓或横截面形状可以被控制为奥格或阶梯形状，以改善短通道效应，并且在不增加电容的情况下降低源极/漏极和延伸电阻。 也可以选择用于不连续膜的材料以在衬底或层内从晶体管沟道施加应力，并提供增加的这种应力水平以增加载流子迁移率。 携带者的流动性可能会与其他有利的影响相结合。

公开(公告)号：US07732874B2

公开(公告)日：2010-06-08

申请号：US11847573

申请日：2007-08-30

申请人： Huilong Zhu ,  Bruce B. Doris ,  Ying Zhang

发明人： Huilong Zhu ,  Bruce B. Doris ,  Ying Zhang

IPC分类号： H01L29/423

CPC分类号： H01L27/1211 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/845 ,  H01L29/785

摘要： A semiconductor structure includes a first finFET and a second finFET. The first finFET and the second finFET may comprise an n-finFET and a p-finFET to provide a CMOS finFET structure. Within the semiconductor structure, at least one of: (1) a first gate dielectric within the first finFET and a second gate dielectric within the second finFET comprise different gate dielectric materials; and/or (2) a first gate electrode within the first finFET and a second gate electrode within the second finFET comprise different gate electrode materials.

摘要翻译： 半导体结构包括第一finFET和第二finFET。 第一finFET和第二finFET可以包括n-finFET和p-finFET，以提供CMOS finFET结构。 在半导体结构内，以下至少一个：（1）第一鳍状FET内的第一栅极电介质和第二鳍状FET内的第二栅极电介质包括不同的栅极电介质材料; 和/或（2）第一鳍状FET内的第一栅电极和第二鳍状FET内的第二栅电极包括不同的栅电极材料。

公开(公告)号：US07452761B2

公开(公告)日：2008-11-18

申请号：US11870436

申请日：2007-10-11

申请人： Huilong Zhu ,  Philip J. Oldiges ,  Bruce B. Doris ,  Xinlin Wang ,  Oleg Gluschenkov ,  Huajie Chen ,  Ying Zhang

发明人： Huilong Zhu ,  Philip J. Oldiges ,  Bruce B. Doris ,  Xinlin Wang ,  Oleg Gluschenkov ,  Huajie Chen ,  Ying Zhang

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/336

CPC分类号： H01L29/7849 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/7842 ,  H01L29/78603 ,  H01L29/78612 ,  H01L29/78618 ,  H01L29/78687

摘要： Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects.

摘要翻译： 场效应晶体管中的沟道深度由包括在半导体材料的层或衬底内形成的不连续膜或层的层内结构限制。 因此，可以以SOI或UT-SOI技术的方式控制通道深度，但是具有较便宜的衬底和更大的通道深度控制的灵活性，同时避免SOI技术的浮体效应特性。 不连续膜的轮廓或横截面形状可以被控制为奥格或阶梯形状，以改善短通道效应，并且在不增加电容的情况下降低源极/漏极和延伸电阻。 也可以选择用于不连续膜的材料以在衬底或层内从晶体管沟道施加应力，并提供增加的这种应力水平以增加载流子迁移率。 携带者的流动性可能会与其他有利的影响相结合。

公开(公告)号：US20080176365A1

公开(公告)日：2008-07-24

申请号：US12077973

申请日：2008-03-24

申请人： Huilong Zhu ,  Bruce B. Doris ,  Xinlin Wang ,  Jochen Beintner ,  Ying Zhang ,  Philip J. Oldiges

发明人： Huilong Zhu ,  Bruce B. Doris ,  Xinlin Wang ,  Jochen Beintner ,  Ying Zhang ,  Philip J. Oldiges

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7855 ,  H01L29/7856

摘要： A method is provided of making a gated semiconductor device. Such method can include patterning a single-crystal semiconductor region of a substrate to extend in a lateral direction parallel to a major surface of a substrate and to extend in a direction at least substantially vertical and at least substantially perpendicular to the major surface, the semiconductor region having a first side and a second side opposite, e.g., remote from the first side. A first gate may be formed overlying the first side, the first gate having a first gate length in the lateral direction. A second gate may be formed overlying the second side, the second gate having a second gate length in the lateral direction which is different from the first gate length. In one embodiment, the second gate length may be shorter than the first gate length. In one embodiment, the first gate may consist essentially of polycrystalline silicon germanium and the second gate may consist essentially of polysilicon.

摘要翻译： 提供了一种制造门控半导体器件的方法。 这种方法可以包括图案化衬底的单晶半导体区域，以在与衬底的主表面平行的横向方向上延伸并且沿至少基本上垂直且至少基本垂直于主表面的方向延伸，半导体 区域具有第一侧和第二侧，例如远离第一侧。 第一栅极可以形成在第一侧上，第一栅极在横向上具有第一栅极长度。 第二栅极可以形成在第二侧上，第二栅极在横向上具有与第一栅极长度不同的第二栅极长度。 在一个实施例中，第二栅极长度可以比​​第一栅极长度短。 在一个实施例中，第一栅极可以主要由多晶硅锗组成，第二栅极可以由多晶硅组成。

公开(公告)号：US20090057765A1

公开(公告)日：2009-03-05

申请号：US11847573

申请日：2007-08-30

申请人： Huilong Zhu ,  Bruce B. Doris ,  Ying Zhang

发明人： Huilong Zhu ,  Bruce B. Doris ,  Ying Zhang

IPC分类号： H01L27/12 ,  H01L21/336

CPC分类号： H01L27/1211 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/845 ,  H01L29/785

摘要： A semiconductor structure includes a first finFET and a second finFET. The first finFET and the second finFET may comprise an n-finFET and a p-finFET to provide a CMOS finFET structure. Within the semiconductor structure, at least one of: (1) a first gate dielectric within the first finFET and a second gate dielectric within the second finFET comprise different gate dielectric materials; and/or (2) a first gate electrode within the first finFET and a second gate electrode within the second finFET comprise different gate electrode materials.

摘要翻译： 半导体结构包括第一finFET和第二finFET。 第一finFET和第二finFET可以包括n-finFET和p-finFET，以提供CMOS finFET结构。 在半导体结构内，以下至少一个：（1）第一鳍状FET内的第一栅极电介质和第二鳍状FET内的第二栅极电介质包括不同的栅极电介质材料; 和/或（2）第一鳍状FET内的第一栅电极和第二鳍状FET内的第二栅电极包括不同的栅电极材料。

公开(公告)号：US06914303B2

公开(公告)日：2005-07-05

申请号：US10650229

申请日：2003-08-28

申请人： Bruce B. Doris ,  Thomas S. Kanarsky ,  Ying Zhang ,  Huilong Zhu ,  Meikei Ieong ,  Omer Dokumaci

发明人： Bruce B. Doris ,  Thomas S. Kanarsky ,  Ying Zhang ,  Huilong Zhu ,  Meikei Ieong ,  Omer Dokumaci

IPC分类号： H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L27/01

CPC分类号： H01L29/66772 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/6656 ,  H01L29/78612 ,  H01L29/78621

摘要： Described is a method for making thin channel silicon-on-insulator structures. The inventive method comprises forming a set of thin spacer abutting a gate region in a first device and a second device region; forming a raised source/drain region on either side of the gate region in the first device region and the second device region, implanting dopants of a first conductivity type into the raised source drain region in the first device region to form a first dopant impurity region, where the second device region is protected by a second device region block mask; implanting dopants of a second conductivity type into the raised source/drain region in the second device region to form a second dopant impurity region, where the first device region is protected by a first device region block mask; and activating the first dopant impurity region and the second dopant impurity region to provide a thin channel MOSFET.